HFC-S Cologne Chip AG, HFC-S Datasheet - Page 12

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3
3.1
3.1.1 Programming of I/O addresses
The HFC-S occupies two consecutive addresses in the I/O map of a PC if it is in ISA-PC mode. It
decodes only the 10 lower address lines as most slot cards do on the ISA-PC bus. On the lower of
both addresses SA0 = 0; on the higher SA0=1.
After every Master Reset (RESET = 1) the I/O address select circuit inside the HFC-S is in hardware
mode. In this mode the HFC-S can not be accessed until it is initialised to an I/O address.
At first one of 15 different I/O addresses must be selected by the 4 inputs IIOSEL0 .. IIOSEL3 as
Table 1 shows:
Table 1: Selected I/O address after reset
The hardware selected I/O address might have an address collision with another I/O device in the PC.
After a hardware reset (RESET = 1) you must first write an I/O address into the HFC-S to set the I/O
address for every further access to the device.
The procedure is as follows:
First you must write the lower 8 bits of the new I/O address you want into the lower address (SA0 =
0) of the hardware selected I/O address. The LSB of the new address is a don't care bit because the
HFC-S always occupies two I/O addresses.
March 1997
Functional description
ISA-PC mode
IIOSEL
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Selected I/O address
processor mode
2D0h
2E0h
2C0h
2E8h
2B0h
3E0h
3E8h
2F8h
210h
200h
320h
278h
310h
330h
300h
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HFC-S