HFC-S Cologne Chip AG, HFC-S Datasheet - Page 25

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3.6
For the FIFO data an 32K x 8 external SRAM is used. A 8K x 8 external RAM is also possible but
not recommended.
The required access time is 80 ns or below.
1024 Byte of the external SRAM are reserved for internal HFC-S use.
Table 3: SRAM size and FIFO depth
To initialise the HFC-S for 8K x 8 SRAM use:
For all further accesses to the CIRM register bit 4 must be set.
March 1997
If you connect the HFC-S with the SRAM you can simplify PCB layout if you permutate
address lines and data lines. If you connect data lines of the SRAM with data lines of the HFC-
S and SR-address lines of the HFC-S with address lines of the SRAM you can do this in any
order.
hint!
external SRAM
External SRAM
- write 18h to the CIRM register
- wait at least 4 clock cycles
- write 10h to the CIRM register
32K x 8
8K x 8
B-channel FIFO depth per
channel and direction
1536 Byte
7680 Byte
D-channel FIFO depth per
direction
512 Byte
512 Byte
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HFC-S