HFC-S Cologne Chip AG, HFC-S Datasheet - Page 37

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

All processor modes:
Reading STATUS_DISBUSY register delays the transition from nobusy to busy until any other
register of the HFC-S is accessed (see Figure 5 on page 26).
This register should be checked for nobusy before accessing any busy-critical register to avoid a
transition from nobusy to busy during a FIFO register access, which may destroy register values.
Busy-critical register are all FIFO registers, the data register of the S/T-part B1_REC/B1_SEND and
B2_REC/B2_SEND, D_REC/D_SEND and the B-channel data register B1_D and B2_D of the
PCM30 bus part.
ISA-PC mode:
It is possible to read the STATUS_DISBUSY register in ISA-PC mode directly by a READ
operation to the port address with SA0='1', but it is necessary to enable the HFC-S going into busy
cycle again after a data port access with SA0='0'.
March 1997
Name
STATUS
Reading the STATUS register clears no bit.
STATUS_DISBUSY
(1Ch)
Bits
0
1
2
3
4
5
6
7
r/w
r
r
r
r
r
r
r
r
(1Dh)
Function
BUSY/NOBUSY status
'1'
'0'
unused, '0'
BUSY/NOBUSY transition interrupt status
'1'
unused, '0'
timer status
'0'
'1'
TE/NT state machine interrupt state
'1'
FRAME interrupt has occured (any data channel interrupt)
all masked D-channel and B-channel interrupts are "ored"
ANY interrupt
all masked interrupts are "ored"
r
All bits are the same as in the STATUS register.
the HFC-S is in BUSY state
the HFC-S is in NOBUSY state, access on all FIFO
functions is now possible
the HFC-S has changed from BUSY to NOBUSY
state, access on all FIFO functions is now possible
This bit is reset by a read of INT_S1.
timer not elapsed
timer elapsed
state of state ma chine has changed
see STATUS register
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HFC-S