HFC-S Cologne Chip AG, HFC-S Datasheet - Page 30

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

March 1997
Name
SQ_REC
SQ_SEND (34h)
CLKDEL
The register is initialized with a '0' after reset. The register should be initialized as follows
before
activating the TE/NT state machine in 12.288 MHz mode:
note!
(34h)
(37h)
TE mode: 0Dh .. 0Fh
Bits
3..0
4
6,5
7
3..0
7..4
3..0
6..4
7
r/w
r
r
r
r
w
w
w
w
w
Function
TE mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3,
NT mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3,
'1'
not defined
'1'
TE mode: Q bits(bit 3 = Q1, bit 2 = Q2, bit 1 = Q3,
NT mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3,
not defined
TE: 4 bit delay value to configure the delay time
NT: Data sample point. The lower the value the earlier
NT mode only
early edge input data shaping
Low pass characteristic of extended bus configurations
can be compensated. The lower the value the earlier input
data pulse is sampled. No compensation means a value of
6 (110b). Step size is the same as for bits 3-0.
master clock frequency selection register
'0'
'1'
a complete S or Q dataword has been received
Reading SQ_REC clears the bit.
ready to send a new S or Q dataword
Writing to SQ_SEND clears the bit.
between receive and transmit direction. The delay of
the
compensated. The lower the value the smaller the
delay between receive and transmit direction (see
Figure 12)
the input data is sampled.
The steps are 130ns at 7.68MHz clock frequency
and 163ns at 12.288MHz clock frequency.
12.288MHz (reset default)
This frequency can only be used in slave mode with
external master clock at PCM30 bus (C4O, F0O).
NT mode: 6Ch
7.68 MHz
external
bit 0 = S4)
bit 0 = Q4)
bit 0 = Q4)
bit 0 = S4)
S/T-interface
circuit
can
30 of 57
HFC-S
be