HFC-S Cologne Chip AG, HFC-S Datasheet - Page 17

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3.3.2 Registers of the S/T section
March 1997
FIFO change
Changing the FIFO must be the last FIFO operation in a non BUSY phase. The new FIFO is
selected after one busy phase.
To select a new FIFO in processor mode a dummy value must be written to the Z1 register
address of this FIFO. The Z1 register is not changed by this operation.
Incrementation of the frame counters (F1, F2)
If the frame counters (F1, F2) are changed it must be in a seperate non BUSY period. That
means writing data to the FIFO or reading data from the FIFO is not allowed during this
period. Also selecting a new FIFO is not allowed. Reading the counters Z1, Z2, F1 and F2 is
allowed before incrementing the frame counter.
Accessability of registers
All operations on the FIFOs and on FIFO control registers and on B- and D-channel data
registers of the S/T and PCM30 bus part are only allowed in the non BUSY period of the HFC-
S.
Status, interrupt and control registers can be read and written at any time.
CIP / I/O-address
00110000 30h
00110001 31h
00110010 32h
00110100 34h
00110111 37h
00111100 3Ch
00111101 3Dh
00111110 3Eh
important!
*)
These registers are read/written automatically by the HDLC FIF O controller (HFC) or
PCM30 bus controller and need not be accessed by the user.
Name
STATES
SCTRL
TEST
SQ_REC
SQ_SEND
CLKDEL
B1_REC
B1_SEND
B2_REC
B2_SEND
D_REC
D_SEND
*)
*)
*)
*)
*)
*)
r/w
r/w
w
w
r
w
w
r
w
r
w
r
w
Function
State of the TE/NT state machine
S/T control register
Power-Up mode
receive register for S/Q bits
send register for S/Q bits
setup of the delay time between receive and
send direction (TE)
receive data sample time (NT)
B1-channel receive register
B1-channel transmit register
B2-channel receive register
B2-channel transmit register
D-channel receive register
D-channel transmit register
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HFC-S