HFC-S Cologne Chip AG, HFC-S Datasheet - Page 28

• Manufacturer Part Number: HFC-S
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

4
4.1
March 1997
Name
STATES
The state machine is stuck to '0' after a reset. Writing a '0' to bit 4 of the STATES register
restarts the state machine.
In this state the HFC-S sends no signal on the S/T-line and it is not possible to activate it by
incoming INFOx.
NT mode: The NT state machine does not change automatically from G2 to G3 if the TE side
sends INFO3 frames. This transition must be activated each time by bit 7 of the STATES
register.
important!
Register bit description
Register bit description of S/T section
Addr.
(30h)
Bits
3..0
4
5
6
7
r/w
r
w
w
r
w
r
w
r
w
r
Function
binary value of actual state (NT: Gx, TE: Fx)
prepare for new state xxxx
'1' loads the prepared state (bit 3..0) and stops the state
'0' restarts the state machine.
not defined
'0'
'1'
not defined
'1' start activation/deactivation as selected by bit 5
This bit is automatically cleared after activation/
deactivation.
not defined
'0'
'1'
not defined
machine. This bit needs to be set for a minimum
period of 5.21 s and must be cleared by software.
(reset default)
After writing an invalid state the state machine goes
to deactivated state (G1, F2)
prepare deactivation
prepare activation
no operation
in NT mode allows transition from G2 to G3.
The bit is automatically cleared after the transition.
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HFC-S