IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 22

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

3.3 Microprocessor interface
General purpose I/O
controlled by the DIR_OUT field in the GPIO register (Table 123 GPIO Register
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
- Parallel microprocessor interface
- Serial microprocessor interface
Five general purpose I/O pins are provided. The direction is independently












8 bit data bus for parallel operation
Byte access
Direct accessed space
Indirect access space is used for most registers
Read operations to a reserved address or reserved bit fields return 0
Write operations to reserved addresses or bit fields are ignored
Compliance to Motorola serial processor interface (SPI) specification
Byte access
Direct accessed space
Indirect access space is used for most registers
Read operations to a reserved address or reserved bit fields return 0
Write operations to reserved addresses or bit fields are ignored
event
primary interrupt level
captured event
interrupted status
enable
interrupted status
Figure 10. Interrupt scheme
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(0x20)). The logical level on a pin is controlled by the LEVEL field in the GPIO
register if DIR_OUT=1, or sensed if DIR_OUT=0. The LEVEL bit monitors the
logic level of any bit selected from the indirect access space if MONITOR_EN
is set high. A bit in the indirect access space can be selected for monitoring by
the by the ADDRESS and BIT fields in the GPIO Link table (Table 124, GPIO
Monitor Table (5 entries 0x21-0x25 for GPIO[0] through GPIO[4])).
time.
Interrupt scheme
cleared by an microprocessor write cycle. A logical one must be written to clear
the flag(s) targeted. A two level interrupt scheme is provided comprising a
primary level and a secondary level.
interrupt. This information is reflected in the primary interrupt register. Interrupt
status can be enabled by associated flags both in the primary and secondary
level of the interrupt scheme.
All GPIO pins must be programmed into or out of monitor mode at the same
Events are captured in interrupt status registers. Interrupt status flags are
The primary level identifies the secondary interrupts sources with a pending
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secondary interrupt level
enable
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INDUSTRIAL TEMPERATURE RANGE
model status
6370 drw22
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INTB
APRIL 10, 2006