IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 7

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
Table 112 - SPI-4 ingress bit alignment counter register (0x02 to 0x0B) ......................................................................................................................... 75
Table 113 - SPI-4 ingress manual alignment phase/result register (0x0C to 0x1F) .......................................................................................................... 75
Table 114 - SPI-4 Egress data lane timing register (register_offset 0x2A) ........................................................................................................................ 75
Table 115 - SPI-4 egress Control Lane Timing register (Register_offset 0x2B) ............................................................................................................... 76
Table 116 - SPI-4 egress data clock timing register (register_offset 0x2C) ....................................................................................................................... 76
Table 117 - SPI-4 egress status timing register (register_offset 0x2D) ............................................................................................................................ 76
Table 118 - SPI-4 egress status clock timing register (register_offset 0x2E) .................................................................................................................... 76
Table 119 - PMON timebase control register (register_offset 0x00) ................................................................................................................................. 77
Table 120 - Timebase register (register_offset 0x01) ...................................................................................................................................................... 77
Table 121 - Clock generator control register (register_offset 0x10) ................................................................................................................................. 77
Table 122 - OCLK and MCLK frequency select encoding ............................................................................................................................................... 77
Table 123 - GPIO register (register_offset 0x20) ............................................................................................................................................................ 78
Table 124 - GPIO monitor table (5 entries 0x21-0x25 for GPIO[0] through GPIO[4]) ....................................................................................................... 78
Table 125 - Version number register (register_offset 0x30) ............................................................................................................................................. 78
Table 126 – JTAG instructions ........................................................................................................................................................................................ 79
Table 127 – Absolute maximum ratings ........................................................................................................................................................................... 79
Table 128 – Recommended Operating Conditions .......................................................................................................................................................... 79
Table 129 – Terminal Capacitance ................................................................................................................................................................................. 80
Table 130 – Thermal Characteristics .............................................................................................................................................................................. 80
Table 131 – DC Electrical characteristics ........................................................................................................................................................................ 81
Table 132 – SPI-3 AC Input / Output timing specifications ................................................................................................................................................ 82
Table 133 – SPI-4.2 LVDS AC Input / Output timing specifications .................................................................................................................................... 84
Table 134 – SPI-4 LVTTL status AC Characteristics ....................................................................................................................................................... 84
Table 135 – REF_CLK clock input ................................................................................................................................................................................. 84
Table 136 – OCLK[3:0] clock outputs and MCLK internal clock ....................................................................................................................................... 84
Table 137 – Microprocessor interface ............................................................................................................................................................................ 84
Table 138 – Microprocessor parallel port Motorola read timing ....................................................................................................................................... 85
Table 139 – Microprocessor parallel port Motorola write timing ....................................................................................................................................... 86
Table 140 – Microprocessor parallel port Intel mode read timing ..................................................................................................................................... 87
Table 141 – Microprocessor parallel port Intel mode write timing ..................................................................................................................................... 88
Table 142 – Microprocessor serial peripheral interface timing ......................................................................................................................................... 89
APRIL 10, 2006
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