IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 37

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

4.4.4 SPI-4 ingress to microprocessor interface
datapath
interface to the microprocessor data capture interface.
device.
length except the last burst of a packet which may be shorter. The control word
is in-band with the data. The burst data enters a SPI-4 ingress buffer. SPI-4 LP
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The diagram below shows the datapath through the device from the SPI-4
The following is a description of the path taken by a burst of data through the
Data enters on the SPI-4 interface in bursts. Bursts are normally of equal
Min: 19.44MHz
Max: 133MHz
8 bit / 32 bit
4 x SPI-3
Figure 29. SPI-4 ingress to microprocessor data capture interface path
t+1
t
t+258
SOP
7
Figure 28. Microprocessor data capture buffer
JTAG
LID Counters Memory
data[255]
data[2]
data[1]
data[0]
length
flags
lid
uproc
EA
SPI-3 /
LID map
Memory
Main
A
ED
37
PAR
address, error information, SOP, and EOP are stored along with the burst data.
The SPI-4 LP address is mapped to a LID. Data is stored in per-LID allocated
buffer segments. The DIRECTION field of the SPI-3 egress port descriptor
(Block_base 0x1700 + Register_offset 0x00 - 0xFF) is used to send this LID
data to the microprocessor port. Data is moved to the capture buffer along with
the LP address, LID, error information, SOP, and EOP.
from the capture buffer through the microprocessor interface.
Chip Counters Memory
The data available bit is set by the PFP. Data and control information are read
EOP
0
t+1
t
t+258
SPI-4 /
LID map
ED
EA
PAR
6370 drw17
address parity error
data parity error
packet error
not used
INDUSTRIAL TEMPERATURE RANGE
6370 drw28
Max:400 MHz
Min: 80 MHz
SPI-4.2
APRIL 10, 2006