IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 32

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 ingress to SPI-3 egress flow control
adjacent device determines which LP to service next according to the status
information it receives from the IDT88P8344. The SPI-4 ingress data arrive in
bursts that are of equal length except for the last burst of a packet which may
be shorter.
The addition of the data may cause an update of the SPI-4 status information
(starving, hungry, satisfied), and may change the SPI-3 STPA, DTPA, or PTPA
signals when in PHY mode.
that the SPI-3 is configured to Link mode, and the case that the SPI-3 is configured
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The SPI-4 control information is transmitted to the adjacent device. The
The SPI-4 burst data is transferred to the per LID allocated buffer segments.
For the control information there are two separate cases to consider: the case
Min: 19.44MHz
Max: 133MHz
8 bit / 32 bit
4 x SPI-3
STATUS
Figure 20. SPI-4 ingress to SPI-3 egress flow control
JTAG
LID Counters Memory
uproc
SPI-3 /
LID map
Memory
Main
A
32
STATUS
to PHY mode. Note that since the SPI-3 physical interfaces are configured
separately, the IDT88P8344 device is able to deal with the case that some of
the LP fragments are to be transmitted on a Link SPI-3 interface and some are
to be transmitted on a PHY SPI-3 interface
the buffer segment pool. In the Link mode an extra consideration is taken to
account – that of the fill level of the ingress FIFOs in the adjacent device.
Backpressure threshold
IDT88P8344 device.
Chip Counters Memory
When in PHY mode, the data is sent according the availability of the data in
- Number of free segments allocated to trigger backpressure for the LP
The diagram below shows the SPI-4 to SPI-3 flow control path through the
SPI-4 /
LID map
6370 drw13a
INDUSTRIAL TEMPERATURE RANGE
STATUS
Max:400 MHz
Min: 80 MHz
SPI-4.2
APRIL 10, 2006