IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 4

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
Figure 1. Typical application: NPU, PHY, and co-processor ............................................................................................................................................. 8
Figure 2. Data path diagram ............................................................................................................................................................................................ 8
Figure 3. Link mode SPI-3 ingress interface ................................................................................................................................................................... 14
Figure 4. PHY mode SPI-3 ingress interface .................................................................................................................................................................. 14
Figure 5. Link mode SPI-3 egress interface .................................................................................................................................................................... 16
Figure 6. PHY mode SPI-3 egress interface ................................................................................................................................................................... 16
Figure 7. Data sampling diagram ................................................................................................................................................................................... 18
Figure 8. SPI-4 ingress state diagram ............................................................................................................................................................................ 19
Figure 9. SPI-4 egress status state diagram ................................................................................................................................................................... 21
Figure 10. Interrupt scheme ........................................................................................................................................................................................... 22
Figure 11. Definition of data flows ................................................................................................................................................................................... 23
Figure 12. Logical view of datapath configuration using PFPs ......................................................................................................................................... 24
Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor ............................................................................................................................. 25
Figure 14. SPI-3 ingress LP to LID map ........................................................................................................................................................................ 27
Figure 15. SPI-4 egress LID to LP map ......................................................................................................................................................................... 28
Figure 16. SPI-3 ingress to SPI-4 egress datapath ........................................................................................................................................................ 28
Figure 17. SPI-3 ingress to SPI-4 egress flow control path ............................................................................................................................................. 29
Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor ............................................................................................................................. 30
Figure 19. SPI-4 ingress to SPI-3 egress datapath ........................................................................................................................................................ 31
Figure 20. SPI-4 ingress to SPI-3 egress flow control ..................................................................................................................................................... 32
Figure 21. SPI-3 ingress to SPI-3 egress datapath ........................................................................................................................................................ 33
Figure 22 . Microprocessor data capture buffer .............................................................................................................................................................. 34
Figure 23. SPI-3 ingress to microprocessor capture interface datapath ........................................................................................................................... 34
Figure 25. Microprocessor interface to SPI-3 egress detailed datapath diagram .............................................................................................................. 35
Figure 24 . Microprocessor data insert buffer ................................................................................................................................................................. 35
Figure 26. Microprocessor data insert buffer .................................................................................................................................................................. 36
Figure 27. Microprocessor data insert interface to SPI-4 egress datapath ....................................................................................................................... 36
Figure 28. Microprocessor data capture buffer ............................................................................................................................................................... 37
Figure 29. SPI-4 ingress to microprocessor data capture interface path .......................................................................................................................... 37
Figure 30. Clock generator ............................................................................................................................................................................................ 39
Figure 31. SPI-3 Loopback diagram .............................................................................................................................................................................. 40
Figure 32. Power-on-Reset Sequence .......................................................................................................................................................................... 41
Figure 33. DDR interface and eye opening check through over sampling ....................................................................................................................... 44
Figure 34. Direct & indirect access ................................................................................................................................................................................. 46
Figure 35. SPI-3 I/O timing diagram ............................................................................................................................................................................... 82
Figure 36. SPI-4 I/O timing diagram ............................................................................................................................................................................... 83
Figure 37. Microprocessor parallel port Motorola read timing diagram ............................................................................................................................ 85
Figure 38. Microprocessor parallel port Motorola write timing diagram ............................................................................................................................ 86
Figure 39. Microprocessor parallel port Intel mode read timing diagram .......................................................................................................................... 87
Figure 40. Microprocessor parallel port Intel mode write timing diagram .......................................................................................................................... 88
Figure 41. Microprocessor serial peripheral interface timing diagram .............................................................................................................................. 89
Figure 42. IDT88P8344 820PBGA package, bottom view .............................................................................................................................................. 94
Figure 43. IDT88P8344 820PBGA package, top and side views .................................................................................................................................... 95
APRIL 10, 2006
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