IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 69

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

9.4.1 Common module block base 0x0000 registers
SPI-4 ingress LP to LID maps (Block_base 0x0000
+ Register_offset 0x00 to 0xFF)
at Block_base 0x0000. The SPI-4 ingress LP to LID maps have read and write
access. The SPI-4 ingress LP to LID maps are used to map SPI-4 ingress logical
ports to logical identifiers used internally.
LID0. Therefore all the LPs that have entries in the calendar tables should be
enabled.
as the register address. Six bits support the 64 simultaneously active LIDs per
SPI-3 physical interface.
Packet Processing Engines. The number in the PFP field selects the PFP
module to be used.
to a LID.
9.4.2 Common module block base 0x0100 registers
SPI-4 ingress calendar_0 (Block_base 0x0100 +
Register_offset 0x00 to 0xFF)
write access. When the SPI-4 ingress calendar_0 is selected, SPI-4 ingress
calendar_0 is in use. There are 256 entries in the SPI-4 ingress calendar_0
to schedule the updating of the FIFO status channel LPs to the attached device.
If less than the maximum 256 LPs are needed on the SPI-4 interface, the
calendar entries should be used for scheduling more frequent status updates
for higher-speed LPs. The value of time-critical LPs must appear multiple times
in the table. For example, a multi-PHY SPI-4 could have OC-48 channels
appear in the calendar at four times the rate of OC-12 channels, since the higher
data rate of the OC-48 channels would benefit from more frequent FIFO status
channel updates. The LP field values range from 0x00 to 0xFF. The
IDT88P8344 and the attached device must have identical calendars for ingress
and the attached egress device. The ingress and egress calendars of the
IDT88P8344 device do not have to match.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
There are 256 SPI-4 ingress LP to LID maps for the SPI-4 ingress interface
Data for an inactive LP having an entry in the calendar is forwarded to
LID
PFP
ENABLE The Enable is used to enable or disable the connection of an LP
The SPI-4 ingress calendar_0 is at Block_base 0x0100 and has read and
ENABLE
PFP
LID
Field
Field
The LID programmed is associated to the LP with the same number
The PFP field is used to select among SPI-4 ingress to SPI-3 egress
0x0=Select PFP Module A
0x1=Select PFP Module B
0x2=Select PFP Module C
0x3=Select PFP Module D
0=LP is disabled
1=LP is enabled
LP
Bits
Bits
5:0
7:6
7:0
8
Length
Length
6
2
1
8
Initial Value
Initial Value
0x00
0x0
0x0
0xFF
69
according to the calendar sequence.
9.4.3 Common module block base 0x0200 registers
SPI-4 ingress calendar_1 (Block_base 0x0200 +
Register_offset 0x00 to 0xFF)
write access. When the SPI-4 ingress calendar_1 is selected, SPI-4 ingress
calendar_1 is in use. There are 256 entries in the SPI-4 ingress calendar_1
to schedule the updating of the FIFO status channel LPs to the attached device.
If less than the maximum 256 LPs are needed on the SPI-4 interface, the
calendar entries should be used for scheduling more frequent status updates
for higher-speed LPs. The value of time-critical LPs must appear multiple times
in the table. For example, a multi-PHY SPI-4 could have OC-48 channels
appear in the calendar at four times the rate of OC-12 channels, since the higher
data rate of the OC-48 channels would benefit from more frequent FIFO status
channel updates. The LP field values range from 0x00 to 0xFF. The
IDT88P8344 and the attached device must have identical calendars for ingress
and the attached egress device. The ingress and egress of the IDT88P8344
do not have to match, however.
according to the calendar sequence.
9.4.4 Common module block base 0x0300 registers
SPI-4 ingress configuration register (Block_base
0x0300 + Register_offset 0x00)
read and write access.
4 ingress interface. The bit fields of the SPI-4 ingress configuration register are
described.
SPI-4_EN
Reserved
Reserved
I_CLK_EDGE
I_DSC
I_INSYNC_THR
I_OUTSYNC_THR
I_CSW_EN
CAL_SEL
I_LOW
LP
The SPI-4 ingress calendar_1 is at Block_base 0x0200 and has read and
LP
The SPI-4 ingress configuration register is at Block_base 0x0300 and has
The SPI-4 ingress configuration register is used to set the state of the SPI-
Field
Field
The LP value programmed schedules a status channel update
The LP value programmed schedules a status channel update
LP
Bits
13:10
9:5
Bits
14
15
16
7:0
0
1
2
3
4
INDUSTRIAL TEMPERATURE RANGE
Length
Length
1
1
1
1
1
5
4
1
1
1
8
Initial Value
APRIL 10, 2006
Initial Value
0x1F
0xF
0xFF
0b0
0x0
0x0
0x0
0x0
0x0
0x0
0b1