IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 24

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

DATAPATH CONFIGURATION
is shown in Figure 12, Logical View of Datapath Configuration Using PFPs.
Two PFPs are associated with each SPI-3 port, one for ingress and one for
LID - Logical Identifier
EN - LID enable flag
BRV - Bit reversal
LP - Logical port
PFP - Packet fragment processor
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
A logical view of datapath configuration using Packet Fragment Processors
SPI-3 Egress LID to LP Map (one of four: ABCD)
SPI-3 Ingress LP to LID Map (one of four: ABCD)
64 LIDs
256 LPs
LP
LID
SPI-3 EGRESS DATA (ONE OF FOUR)
SPI-3 INGRESS DATA (ONE OF FOUR)
EN
EN
BRV
BRV
Figure 12. Logical view of datapath configuration using PFPs
[LID] = LP | EN | BRV
[LP] = LID | EN | BRV
(ONE OF FOUR: ABCD)
(ONE OF FOUR: ABCD)
(ONE OF FOUR: ABCD)
PFP AND MEMORY
(ONE OF FOUR: ABCD)
(ONE OF FOUR: ABCD)
PFP AND MEMORY
(ONE OF FOUR: ABCD)
PFP AND MEMORY
(ONE OF FOUR: ABCD)
PFP AND MEMORY
PFP AND MEMORY
(ONE OF FOUR: ABCD)
PFP AND MEMORY
PFP AND MEMORY
PFP AND MEMORY
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egress. Logical ports are mapped internally into Logical Identifiers (“LIDs”, “LID
Map”) for the control of each per-LID data flow to each physical port, logical port,
memory queue size, and backpressure threshold (watermark), by program-
ming the LID register files.
[LP] = LID | PPE | EN
[LID] = LP | EN
SPI-4 EGRESS DATA
SPI-4 Egress LID to LP Map
INDUSTRIAL TEMPERATURE RANGE
SPI-4 Ingress LP to LID Map
SPI-4 INGRESS DATA
LP
LID
A/B/
C/D
6370 drwXB
EN
APRIL 10, 2006
EN
256 LIDs
256 LPs