IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 72

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

0x0300 + Register_offset 0x0F. The SPI-4 ingress diagnostics register has
read and write access. The SPI-4 ingress diagnostics register is used in port
diagnostics to force continuous training on the SPI-4 ingress status interface,
insert a DIP-2 error on the SPI-4 ingress status interface, and read the number
of DIP-2 errors seen on the SPI-4 egress status interface.
ous training on the SPI-4 ingress status interface.
2 errors on the SPI-4 ingress status interface programmed into the I_DIP_NUM
field. After the DIP-2 errors are inserted, the I_ERR_INS field will clear itself.
programmed into the I_DIP_NUM field on the SPI-4 egress status interface..
SPI-4 ingress DIP-4 error counter (Block_base
0x0300 + Register_offset 0x10)
0x0300 + Register_offset 0x10. The SPI-4 ingress DIP-4 error counter has
read access, and automatically clears itself after a read. The SPI-4 ingress DIP-
4 error counter is used in port diagnostics to verify the integrity of the SPI-4
ingress data path.
the SPI-4 egress status interface. The DIP_4 field saturates at the value
0xFFFF, and is automatically cleared after reading to re-start DIP-4 error
counter accumulation.
SPI-4 ingress bit alignment control register
(Block_base 0x0300 + Register_offset 0x11)
0x0300 + Register_offset 0x11. The SPI-4 ingress bit alignment control register
has read and write access. The SPI-4 ingress bit alignment control register is
used to overrule the automatically selected bit phase alignments and go to
manual mode. In manual mode, the PHASE_ASSIGN field [Block_base 0x0800
+ Register_offset 0x0c – 0x1F] now defines the selected phase.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The SPI-4 ingress diagnostics register is addressed from Block_base
I_FORCE_TRAIN
I_ERR_INS
I_DIP_NUM
The I_DIP_NUM field is used to create the number of DIP-2 errors
The SPI-4 ingress DIP-4 error counter is addressed from Block_base
DIP_4 The DIP_4 field is used to read the number of DIP-4 errors seen on
The SPI-4 ingress bit alignment control register is addressed from Block_base
FORCE The FORCE field is used to manually align the SPI-4 ingress data.
DIP_4
FORCE
Field
Field
0=Normal status channel operation
1=Force continuous training on the SPI-4 ingress status interface
0=Normal status channel operation
1= Insert DIP-2 errors on the SPI-4 ingress status interface
0=Normal bit alignment operation
the PHASE_ASSIGN field.
1= Force to manual bit alignment mode on SPI-4 ingress data using
The I_ERR_INS field is used to insert the number of DIP-
The I_FORCE_TRAIN field is used to force continu-
Bits
15:0
Bits
0
Length
Length
16
1
Initial Value
Initial Value
0
0
72
SPI-4 ingress start up training threshold register
(Block_base 0x0300 + Register_offset 0x12)
Block_base 0x0300 + Register_offset 0x12. The SPI-4 ingress start up training
threshold register has read and write access. The SPI-4 ingress start up training
threshold register is used to set the number of consecutive training patterns that
will lead to OUT_OF_SYNCH on the SPI-4 ingress data. If the STRT_TRAIN
field is set to zero, then the OUT_OF_SYNCH feature is disabled.
consecutive training patterns that will lead to OUT_OF_SYNCH on the SPI-4
ingress data interface.
9.4.5 Common module block base 0x0400 registers
SPI-4 egress LID to LP map (Block_base 0x0400)
interface. The entries are at Block_base 0x0400 + LID. For example, LID 0x00
is at Block_base 0x0400 + 0x00. A SPI-4 egress LID to LP map has read and
write access. A SPI-4 egress LID to LP map is used to map a logical identifier
used internally to a SPI-4 egress logical port.
LID0. Therefore all the LPs that have entries in the calendar tables should be
enabled.
the register address. Eight bits support the 256 possible LPs on the SPI-4
physical interface. 256 simultaneously active LPs are supported by the
IDT88P8344 device.
9.4.6 Common module block base 0x0500 registers
SPI-4 egress calendar_0 (Block_base 0x0500)
write access. When the SPI-4 egress calendar_0 is selected, calendar_0 is
in use. There are 256 entries in the SPI-4 egress calendar_0 to schedule the
The SPI-4 ingress start up training threshold register is addressed from
STRT_TRAIN
There are 256 entries in the SPI-4 egress LID to LP map for the SPI-4 egress
0x00 - 0x3F of the LID map is for Module A LIDs 0x00 - 0x3F
0x40 - 0x7F of the LID map is for Module B LIDs 0x00 - 0x3F
0x80 - 0xBF of the LID map is for Module C LIDs 0x00 - 0x3F
0xC0 - 0xFF of the LID map is for Module D LIDs 0x00 - 0x3F
Data for an inactive LP having an entry in the calendar is forwarded to
LP The LP programmed is associated to the LID with the same number as
EN The EN bit is used to enable or disable the connection of a LID to an LP.
The SPI-4 egress calendar_0 is at Block_base 0x0500 and has read and
STRT_TRAIN
LP
EN
LP
Field
Field
Field
0=LP is disabled
1=LP is enabled
The STRT_TRAIN field is used to set the number of
Bits
Bits
Bits
7:0
7:0
7:0
INDUSTRIAL TEMPERATURE RANGE
8
Length
Length
Length
8
8
1
8
APRIL 10, 2006
Initial Value
Initial Value
Initial Value
0x00
0b0
0xFF
0