IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 52

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

Software reset
Write a “1” to the SW_RESET bit to initiate the software reset. The SW_RESET
bit will clear to a “0” after the chip has initialized itself. The INIT_DONE bit is set
to a “1” when the initialization following reset has completed. The software reset
is the same as the hardware. The Reserved field must be set to 0.
has completed.
SPI-4 status register (0x22 in the direct accessed
space)
access, and interrupt status fields are cleared by a microprocessor write cycle,
where a logical one must be written to clear the field(s) targeted.
only be active if the SPI-4 field is active in the Primary Interrupt Status Register
(Direct 0x2C).
synchronization to in synchronization condition interrupt indication.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
I_DIP_ERR_I
I_SYNCH_I
I_BUS_ERR_I
SPI4_INACTIVE_TRANSFER_I
DCLK_UN_I
E_DIP_ERR_I
E_SYNCH_I
SCLK_UN_I
The software reset bit is writable from the direct accessed memory space.
The Initial Value column in this document is the value of the register after reset
SW_RESET Setting the SW_RESET bit initiates a software reset of the chip.
INIT_DONE Status indication bit following a reset.
The SPI-4 Status Register (0x22 in the direct accessed space) has read
The SPI-4 Status Register is a secondary interrupt status register and can
I_DIP_ERR_I
0=No errors
1=One or more DIP-4 errors have been registered on the SPI-4 ingress
I_SYNCH_I
0=No detection, still not in synchronization
SW_RESET
INIT_DONE
Reserved
Field
Field
The SW_RESET bit is self-clearing.
SPI-4 ingress DIP-4 error interrupt indication.
SPI-4 ingress data path has transitioned from out of
0=No operation is performed
1=Initiate a software reset
0=Chip has not completed initialization following reset
1= Chip has completed initialization following reset
Bits
7:2
0
1
Length
Bits
0
1
2
3
4
5
6
7
1
1
6
Length
1
1
1
1
1
1
1
1
Initial Value
0
0
0
Initial Val
0
0
0
0
0
0
0
0
52
from in synchronization to out of synchronization
rupt indication.
to an unavailable condition interrupt indication.
4 egress status channel.
synchronization to an in synchronization condition interrupt indication.
from in synchronization to out of synchronization
to an unavailable condition interrupt indication.
(E_SCLK_T). Therefore, for LVTTL mode the software should ignore the
SCLK_UN field in the SPI-4 Status Register.
SPI-4 enable register (0x23 in the direct accessed
space)
and write access. SPI-4 Enable Register is used to bitwise enable the interrupts
in the SPI-4 Status Register.
I_DIP4_ERR_EN
I_SYNCH_EN
I_BUS_ERR_EN
SPI4_INACTIVE_TRANSFER_EN
DCLK_UN_EN
E_DIP_ERR_EN
E_SYNCH_EN
SCLK_UN_EN
1=Transition from out of synchronization to in synchronization, or transition
I_BUS_ERR_I SPI-4 ingress bus error interrupt indication.
0=No errors
1=One or more bus errors have been registered on the SPI-4 ingress
SPI4_INACTIVE_TRANSFER_I
0=No indication
1=One or more inactive transfers have been registered on the SPI-4 ingress
DCLK_UN_I
0=No detection, I_DCLK is available
1=I_DCLK transitioned from available to an unavailable state
E_DIP_ERR_I SPI-4 egress DIP-2 error interrupt indication on the SPI-
0=No errors
1=One or more DIP-2 errors have been registered
E_SYNCH_I
0=No detection, still not in synchronization
1=Transition from out of synchronization to in synchronization, or transition
SCLK_UN_I
In LVTTL mode the Bridgeport does not detect the SPI-4 egress status clock
0=No detection, E_SCLK is available
1=E_SCLK transitioned from available to an unavailable state
The SPI-4 Enable Register (0x23 in the direct accessed space) has read
I_DIP4_ERR_EN SPI-4 ingress DIP-4 error interrupt indication enable.
0=Disable DIP-4 error interrupt
1=Enable DIP-4 error interrupt
Field
SPI-4 ingress data clock has transitioned from available
SPI-4 egress status channel has transitioned from out of
SPI-4 egress status clock has transitioned from available
INDUSTRIAL TEMPERATURE RANGE
Bits
SPI-4 ingress inactive transfer inter-
0
1
2
3
4
5
6
7
Length
1
1
1
1
1
1
1
1
APRIL 10, 2006
Initial Val
0
0
0
0
0
0
0
0