IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 30

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

4.2 SPI-4 to SPI-3 datapath and flow control
are provided, all connected to one SPI-4 ingress interface.
buffers. A packet fragment processor transfers complete packet bursts from the
SPI-4 ingress port buffers to memory segments previously reserved on a per-
LP basis in the buffer segment pool. The SPI-4 ingress port buffer watermarks
and the per-LP free buffer segment threshold information is combined to produce
SPI-4 ingress FIFO status (per-LP starving, hungry, or satisfied) towards the
attached SPI-4 device. Per-LP buffer segment threshold information is used to
produce FIFO status information for the attached SPI-3 device. Packets or
packet fragments are forwarded to the SPI-3 interface when a packet is complete
or a predefined number of bytes have been received. Packets or packet
fragments received on one SPI4 logical port are cross connected to an SPI3
logical port through an intermediate mapping to a Link identification, or LID. Its
mode of operation is similar to the SPI-3 ingress to SPI-4 egress packet fragment
processor, with the following differences:
SPI-4 buffers, redirect buffers, and insert buffers.
to SPI-4 redirect path.
unavailable status information to its packet fragment processor.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
Four Packet Fragment Processor modules from SPI4 ingress to SPI-3 egress
Packet bursts from the SPI-4 ingress are received into the SPI-4 ingress port
1) The PFP4-3 data input has three sources, listed in descending priority:
2) The PFP3-4 data output has only three destinations. There is no SPI-3
Each SPI-3 interface feeds ingress buffer available or ingress buffer
SPI-3
Egress
FIFO Status
SPI-3 egress port
Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor
buffers
uP
capture
buffer
buffer segment pool
30
threshold, the SPI-4 status is moved to starving for that LP. If the number of free
segments available to a LP exceeds the hungry but not the starving threshold,
the SPI-4 status is moved to hungry for that LP. If the hungry threshold is not
exceeded, the SPI-4 FIFO status channel will indicate satisfied for that LP.
SPI-4 ingress to SPI-3 egress datapath
device from the SPI-4 ingress to a SPI-3 egress.
equal length except the last burst of a packet which may be shorter. The control
word is in-band with the data. Burst data enters a SPI-4 ingress buffer. SPI-4
LP address, error information, SOP, EOP are stored with the burst data. A SPI-
4 LP address is mapped to a Logical IDentifier (LID). The burst is stored in per
LID allocated buffer segments reserved from the buffer segment pool.
descriptor table (64 entries)) is consulted, and it determines to send this LID to
a prescribed SPI-3 egress port.
of the LP and the availability of a complete fragment. Data is moved to the
appropriate SPI-3 egress buffer along with the LP address. SPI-3 LP address,
error information, SOP, and EOP information is stored with the packet fragment.
Next, data is transmitted in packet fragments over the selected SPI-3 interface.
If the number of free segments available to a LP exceeds the starving
The following is a description of the path taken by a burst of data through the
Data enters on the SPI-4 ingress interface in bursts. Bursts are normally of
The appropriate SPI-3 egress control register (Table 80 - SPI-3 egress port
The selection of which LP is to be transmitted next is dependent on the status
insert
buffer
SPI-4 ingress port
uP
buffers
INDUSTRIAL TEMPERATURE RANGE
ingress PFP
Associated
FIFO Status
redirect
buffers
SPI-3
SPI4 Ingress
6370 drw37
APRIL 10, 2006