IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 45

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

high and low level phase are symmetrical. For random input data on each lane,
the counters Cn=CNTn(t)+CNTn(t+1)+. . .+CNTn(t+T), where T is a time
window to do the statistics computation, will increment as follows:
the transition position of a clock and define the position.
Software for implementing the Eye-Opening Check
ing an eye-opening check. The SPI-4 interface has 16 data lanes and one
control lane on ingress, 2 status lanes on egress, making a total of 19 lanes.
above, based on which the signal statistics are computed. It is recommended
to use the default value. The MEASURE_BUSY bit indicates the status of the
internal measurement operation.
the maximum counter value is 0x3ff.
of the SPI-4 interface.
even a small jitter value of 1ps on the lane or the clock, may cause eye closing
that can be detected by observing the counter values. In an ideal case with zero
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
Counter
Value
For an ideal case, there is zero jitter on clock an data, zero skew, the clock
Where P and K are non-zero and need to be a large enough value mark
In the IDT88P8344, a set of diagnostic registers are provided for implement-
The SPI-4 ingress bit alignment window register defines the window T stated
Because the SPI-4 ingress bit alighnment counter register has a 10-bit width,
If the counter values of a lane are:
The eye open is perfect; there is very good signal integrity on input signals
In each sample position represents a “tap”. Depending on the delay in a lane,
#define SPI-4_ingress_lane_measure_register 0x8801 /* register address in SPI exchange device*/
#define SPI-4_ingress_bit_alignment_counter_register(0) 0x8802
#define SPI-4_ingress_bit_alignment_counter_register(1) 0x8803
#define SPI-4_ingress_bit_alignment_counter_register(2) 0x8804
#define SPI-4_ingress_bit_alignment_counter_register(3) 0x8805
#define SPI-4_ingress_bit_alignment_counter_register(4) 0x8806
#define SPI-4_ingress_bit_alignment_counter_register(5) 0x8807
#define SPI-4_ingress_bit_alignment_counter_register(6) 0x8808
#define SPI-4_ingress_bit_alignment_counter_register(7) 0x8809
#define SPI-4_ingress_bit_alignment_counter_register(8) 0x880a
#define SPI-4_ingress_bit_alignment_counter_register(9) 0x880b
For lane=0 to K step 1
{
}
0, 0, 0x3ff, 0, 0, 0, 0, 0x3ff, 0, 0
write #lane, SPI-4_ingress_lane_measure_ register
wait until BUSY=0
0x8801*/
for i=0 to 9 step 1
{
}
print C(0), C(1), C(2), C(3), C(4), C(5), C(6), C(7), C(8), C(9)
C
0
0
C
read C(i), SPI-4_ingress_bit_alignment_counter_register(i)
0
1
C
P
2
C
/*the number K depend on status mode: K=18 in LVDS status mode*/
/* BUSY: bit 8 of SPI-4_ingress_lane_measure_register, at address
0
/*
3
C
0
4
C
0
5
C
0
6
C
K
7
45
to be read, a write to this register triggers the eye-opening check process to the
selected lanes and the MEASURE_BUSY bit will be set accordingly indicating
the measuring process is active. The MEASURE_BUSY bit is cleared internally
which indicates that the measuring process is complete. The measured result
of counters C
counter registers.
ingress bit alignment counter registers.
delay, if the jitter on a data lane or clock is less than one tap interval (peak to
peak), the jitter will not be reflected in counters. While the eye open check can
indicate excessive jitter there are limitations in providing a accurate measure-
ment using this method.
each 2 bits within a clock cycle the sampled signal position will be correct and
the interface will function correctly. The more counters that have zero values,
the better the eye opening.
K=16otherwise */
The SPI-4 ingress lane measure register selects the lane statistics counters
Note that there is one SPI-4 ingress lane measure register and 19 SPI-4
The following pseudo code shows how to check the eye opening:
Theoretically as long as one tap accumulates enough non-zero samples for
C
0
8
C
0
0
9
through C
9
will be available in the SPI-4 ingress bit alignment
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006