IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 31

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 ingress interface configurable parameters:
SPI-4 port can be enabled or disabled.
4 words are then aligned among each other to produce valid words. This is
performed both on the data channel and the status channel. The bit alignment
algorithm runs as long as the interface is active. The word alignment algorithm
is run during training intervals.
SPI-4 ingress per-LID configurable parameters
SPI-4 to SPI-3 LID map
SPI-4 ingress packet length check
minimum and maximum packet length. The minimum packet length can be set
from 0 to 255 bytes in one byte increments. The maximum packet length can
be set from 0 to 16,383 bytes in one byte increments. Packets shorter or longer
than set by these parameters will be optionally counted in the short or long packet
counter for that LID.
SPI-3 egress configurable parameters
Length of SPI-3 packet fragment
mable to an equal length with the possible exception of an EOP fragment which
may be shorter.
SPI-3 egress poll length
the packet level polling mode
from [0 up to POLL_LENGTH] to find logical ports that can accept data
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The IDT88P8344 can interface to either a Link or a PHY layer device. The
The SPI-4 ingress bits are aligned with the ingress clock. In addition, the SPI-
256 entries, one per SPI-4 LP
SPI-3 physical interface identifier
SPI-3 LID
Enable bit per LID
Each LID on the SPI-4 ingress interface has the ability to be programmed for
All packet fragments from a particular SPI-3 physical interface are program-
Applies when the SPI-3 interface is acting as a Link layer device when using
Causes polling of the PHY for the logical ports associated with LIDs ranging
Poll range is 0-63 LPs.
Min: 19.44MHz
Max: 133MHz
8 bit / 32 bit
4 x SPI-3
Figure 19. SPI-4 ingress to SPI-3 egress datapath
JTAG
LID Counters Memory
uproc
SPI-3 /
LID map
Memory
Main
A
31
SPI-3 egress per-LID configurable parameters
following paragraphs describe these parameters.
SPI-3 egress LID to LP map
SPI-3 egress multiple burst enable
feature is included to relieve systems with long latency between updates. When
this feature is not enabled, only one burst per LP is allowed into the round robin
SPI-3 egress buffers at a time.
SPI-4 ingress to SPI-3 egress data memory
SPI-3 egress control
memory. The function a SPI-3 egress port descriptor table is to define where
data goes after leaving the main data memory. There are three configurable
options:
Maximum number of memory segments
interface to the SPI-3 interface.
Chip Counters Memory
Many parameters to control the flow of data are programmable per LID. The
one map per SPI-3 physical port
64 entries per map, one per LID
LP enable bit per LP
Bit reversal enable per LP
Multiple Burst Enable allows more than one burst to be sent to an LP. This
There is a SPI-3 egress port descriptor table for the paths out of the data
SPI-3 egress
Microprocessor Interface Capture
Discard
Defines the largest Buffer available to an LP / LID
Each segment is 256 bytes
Range 1 – 508 in increments of one segment
The figure below shows the datapath through the device from the SPI-4
SPI-4 /
LID map
6370 drw13
INDUSTRIAL TEMPERATURE RANGE
Max:400 MHz
Min: 80 MHz
SPI-4.2
APRIL 10, 2006