AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 14

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

3.4 Interrupt Sources: USIU Internal Devices
The SIEL (USIU interrupt edge level register) contains bits for IRQ[0:7] input pins to specify if the inter-
rupt is caused by a falling edge (ED=1) or simply a low level (ED=0).
Typically a falling edge interrupt input (ED=1) is used. In this case, the appropriate bit in the SIPEND
must be cleared in the interrupt service routine when a falling edge interrupt occurs.
Low level interrupt inputs (ED=0) are used for wired-OR situation of multiple sources on one line. When
an interrupt of this type occurs, the interrupt service routine must ensure the interrupt line is returned to
the inactive high state before exiting the interrupt service routine.
All interrupt sources except external IRQ pins must be given level assignments in some register (see
Section Appendix A Table of Potential Interrupt
rupt source to an input of the USIU interrupt controller. When the interrupt source attempts to initiate an
interrupt request, its level to the USIU interrupt controller becomes active. The interrupt controller will
recognize the interrupt if:
• Interrupts are enabled in the MSR[EE] bit
• The level is not blocked in the SIMASK register
• The level is not competing with a higher priority interrupt request.
Levels in the USIU interrupt sources are assigned in an 8-bit field with the format in
mistake made is to attempt to use a binary value of the level instead of the pattern shown in
The USIU has four interrupt sources:
Some sources can cause an interrupt from more than one condition, but each has only one interrupt
level. For example, the time base has one level but can cause an interrupt when it matches either one
of two time base reference registers TBREFA or TBREFB. Each time base reference has its own inter-
rupt enable bit and each has its own status bit. If both are enabled, the time base interrupt service rou-
tine must check the status bits to determine which caused the interrupt.
1. Programmable interrupt timer (PIT)
2. Time base (TB)
3. Real-time clock (RTC)
4. Phase lock loop change of lock (PLL)
A software watchdog can also cause a NMI reset. IRQ[0] is ALWAYS edge trig-
gered.
Freescale Semiconductor, Inc.
Level Assignment
Table 9 IUSIU Interrupt Level Assignments
For More Information On This Product,
Rev. 0, 26 July 2001
—
MPC555 Interrupts
0
1
2
7
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NOTE
Binary Value
10000000
01000000
00100000
00000001
Sources). These level assignments map the inter-
—
Hex Value
0x80
0x40
0x20
0x01
—
Table
9. A common
MOTOROLA
Table
9.
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