AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 5

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

2.5.1 System Reset: Vector Offset = 0x100
2.5.2 NMI interrupt: Vector Offset = 0x100
2.5.3 Machine Check: Vector Offset = 0x200
2.5.4 Floating-Point Unavailable: Vector Offset = 0x800
2.5.5 Decrementer: Vector Offset = 0x900
The reset exception is taken from a number of sources as listed below. For more information, see
TION 7, RESET,
• Reset pins PORESET, HRESET, or SRESET
• IRQ[0], which is a non-maskable interrupt pin
• Clock: loss of lock or on-chip clock switch
• Software watchdog timer (if SYPCR[SWRI] is clear)
• Checkstop condition
• Debug or JTAG port
Depending on the source of reset, three levels of accompanying hardware initializations occur: power-
on, hard or soft. Thus, it must be remembered that from executing from vector 0x100 the controller can
be in different states, appropriate care must be used. To check the source of reset, and thus the impli-
cations to the MPC555, it is possible to check the RSR register. The RSR bits can only be cleared by
power-on and software writing a “1” to them.
A non-maskable interrupt (NMI) is generated from one of two sources:
• The software watchdog timer (if the SYPCR[SWRI] bit is set)
• The IRQ[0] pin
When an NMI exception occurs, the reset vector offset is used. Consequently it may be necessary to
check if it was a NMI that occurred because, unlike the reset, many of the initialization events to
registers do not occur. The NMI is taken asynchronously to the program flow, can never be masked
and has the highest priority.
Because NMI is not maskable, there is risk that an NMI exception may not be recoverable. Therefore it
should not be used for normal applications but used only for emergency.
This separate exception informs of any memory access violations such as non-existent addresses, data
errors or a violation of the memory protection type. The exception can occur for both internal and exter-
nal memory areas. For a machine check exception to occur, it must be enabled by setting the MSR[ME]
bit before the memory violation takes place. Otherwise (if MSR[ME]=0) no machine check exception is
generated, but the checkstop state is entered. The behavior of the checkstop state is determined by the
PLPRCR[CSR] bit.
As the name suggests, the vector occurs when floating-point instructions are being used without the
floating point unit being enabled. A common cause of this is when software attempts floating-point in-
structions during an exception routine, but the floating-point unit was disabled at the beginning of the
exception routine. Therefore, it can be used to trap and re-enable the floating-point unit when not done
so in another exception service routine.
The decrementer and closely associated time base counters are defined within the PowerPC architec-
The IRQ[0] can generate an interrupt to the core as well, this operation is undes-
ired. IRQ[0] should always be masked in the SIPEND register.
in the
MPC555 User’s Manual
Freescale Semiconductor, Inc.
For More Information On This Product,
Rev. 0, 26 July 2001
MPC555 Interrupts
Go to: www.freescale.com
NOTE
(MPC555UM/AD).
MOTOROLA
SEC-
5