AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 19

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

4 Initialization Steps
4.1 Step 1: Module Specific Initialization
4.2 Step 2: Level Assignment
4.3 Step 3: Enable Interrupt
4.4 Step 4: Set Appropriate Mask Bits in SIMASK
4.5 Final Step: Setting MSR[EE] and MSR[RI] Bits
Each interrupt source must be initialized before all interrupts can be enabled in the machine state reg-
ister, EE bit. Initialization consists of four steps: module specific initialization, level assignment, enabling
the interrupt source, and setting the interrupt mask in the SIU interrupt controller.
The initialization steps below are broken out for illustrating completeness, and do not illustrate the most
efficient programming methods.
Each interrupt source will need to have its own general initialization of its module. Complete module
initialization is outside the scope of this application note. Examples of some module specific initializa-
tions are:
• Interrupt Pins: specify edge or level detection
• Timers: specify clock input selection, clock prescaler value, pre-loading value
• Serial I/O: specify baud rate, queue management parameters
• QADC: specify queue management parameters
• TPU, MIOS: specify function assignment, function specific parameters
The system designer must make careful assignment of levels to each interrupt source. Key points to
remember as discussed in the
sections are summarized here:
• Lower level numbers have higher priority
• External interrupt pins do not have level assignments but have a fixed priority
• To reduce latency, each interrupt source should be mapped to its own level if possible
• When UIMB peripherals have levels over 7, the UMCR[IRQMUX] field must be set to enable
The registers used for level assignments for each interrupt source are listed in
Table of Potential Interrupt
and 2-bit fields to assign levels as discussed in the section
ripherals.
Each interrupt source other than IRQ pins must be enabled. The enable control bit for the sources are
listed in
All appropriate USIU interrupt controller levels 0:8 must have their mask bits set (enabled) in the SI-
MASK register.
After all the interrupt sources have been initialized to the previous steps, the enable external interrupts
[EE] bit must be set for interrupts to be recognized and recoverable interrupt [RI] set to tell exceptions
the state is recoverable. This is easily done by using the EIE special purpose register as mentioned in
the prior
the MSR[EE] and MSR[RI] bits. Writing is accomplished by using the mstpr instruction.
Example: mtspr EIE, r0
appropriate multiplexing.
Section Appendix A Table of Potential Interrupt
Section 3.1 PowerPC Core Interrupt
Freescale Semiconductor, Inc.
For More Information On This Product,
Sources. Remember, level registers use either a single 5-bit field or 3-bit
Section 3.2 USIU Interrupt Controller
Rev. 0, 26 July 2001
MPC555 Interrupts
Go to: www.freescale.com
section. Writing any value to the EIE register sets both
Section 3.6 Interrupt Sources: UIMB Pe-
Sources.
and
Section 3.5 UIMB Module
Section Appendix A
MOTOROLA
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