AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 6

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

2.5.6 Floating-Point Assist: Vector Offset = 0xE00
2.5.7 Data and Instruction Breakpoints Exception: Vector Offsets = 0x1C00 and 0x1D00
2.5.8 Maskable and Non-Maskable External Breakpoints Exceptions:
2.6 Recoverable Exception [Interrupt]
ture as 32-bit decrementing and 64-bit incrementing counters. Both counters are only accessible as
special-purpose register accesses and thus cannot be accessed as memory mapped modules. The ma-
jor difference between them is that the time base counter causes an interrupt on offset 0x500 while the
decrementer provides a separate exception at 0x900.
The decrementer will cause an exception when it rolls over from all zeros to the LSB being set high
again to begin the counting process. The count value is configurable through the DEC register (SPR22)
but must be set through the use of the special MFSPR and MTSPR (move from and move to special
purpose register) PowerPC instructions. On the MPC555, the decrementer clock is a subdivision of the
processor clock. The clock source is either the system clock (divided by 16) or the oscillator clock input
(divided by 4 or 16) as specified in the time base source bit (TBS) in the system clock control register
(SCCR). The decrementer is enabled by the TBE bit in the time base status and control register (TB-
SCR).
Although, there are other counters on the MPC555, the decrementer has the advantage of requiring no
decoding for the exception vector and thus is useful for frequently called timer periods, such as an op-
erating system ticks.
The purpose of this exception is to provide a mechanism to call a software envelope (routines) to fully
implement the IEEE-754 floating-point specification. The software routine handles a number of extreme
conditions that are rare and expensive to implement in hardware. The software routine will impact the
size and the effect on the average instruction processing speed.
Non-IEEE mode is typically recommended for embedded applications because of faster execution.
However, non-IEEE mode can not cause this execption. See
information.
In most cases, these exception vectors are not used. They are reserved for a non-BDM debugger (soft-
ware monitor) or some user-specific exception. Noirmally the BDM is entered as a result of a data and
instruction breakpoint, then the MPC555 executes instructions received serially via the BDM link. For
more information, see
(MPC555UM/AD).
Vector Offsets = 0x1E00 and 0x1F00
As stated in
and
debugger (software monitor) or some user-specific exception. Typically the BDM is entered as a result
of a maskable and non-maskable external breakpoint, then the MPC555 executes instructions received
serially via the BDM link. For more information, see
MPC555 User’s Manual
Sometimes when an exception occurs it may not be possible to recover the machine state. The recov-
erable interrupt bit in the machine state register, MSR[RI], is a status bit indicating this condition
If a non-maskable exception occurs such as reset, breakpoints or a machine check, software can poll
the MSR[RI] bit to determine if the machine can recover its state. This bit changes state either automat-
ically by hardware or manually under software control.
0x1D00, these exception vectors are not used in most systems. They are reserved for a non-BDM
Section 2.5.7 Data and Instruction Breakpoints Exception: Vector Offsets = 0x1C00
SECTION 21, DEVELOPMENT SUPPORT,
Freescale Semiconductor, Inc.
(MPC555UM/AD).
For More Information On This Product,
Rev. 0, 26 July 2001
MPC555 Interrupts
Go to: www.freescale.com
SECTION 21, DEVELOPMENT SUPPORT,
Section 7 Examples of Initialization and In-
RCPURM/AD Section 3.4.3
in the
MPC555 User’s Manual
MOTOROLA
for further
in the
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