AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 24

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

6.5 Step 5: Branch to Interrupt Handler and Execute It
6.6 Step 6: Restore Contexts
6.7 Step 7: Return to Program
The SIVEC[INTERRUPT CODE] can efficiently be used as an index into a jump table. A jump table will
contain pointers to the various interrupt handlers for each source. By adding the index to the address
of the start of the table, the address of the source’s handler routine can be loaded into a register that
can be used for branching, like the LR.
“Interrupt handler” here is defined as interrupt service routine code specific to a module.
Once the address of the interrupt source’s handler routine is loaded in a register, then we can branch
to it. The architecture allows branching from the CTR or LR registers, so the address must be loaded
into one of them.
If the interrupt handler routine is written in C, the program will return to the next instruction after the
above “blrl” at the end of the routine. If the routine is written in assembler, then the last instruction needs
to be:
Restoring contexts includes anything saved on the stack in steps 1 and 3, such as SRR0:1, gprs, etc.
These are combined in one step here. Sample lines to restore some registers are:
Care must be taken to clear the MSR[RI] bit before restoring SRR0:1 to indicate an exception during
restoring these registers can result in an unrecoverable condition.
As mentioned before, the load multiple word (lmw) or load string word immediate (lswi) instructions can
shorten restoring contexts.
A single instruction, return from interrupt, will exit the interrupt exception routine. This instruction re-
stores the MSR from SRR1, which can re-enable exceptions such as external interrupts, the (MSR[EE]
bit), floating-point unit (MSR[FP] bit) and others in the MSR. The instruction pointer gets loaded with the
address in SRR0 and processing branches to that location. Example:
1. Check the INTERRUPT CODE field in the USIU interrupt controller’s SIVEC register, see
2. If the interrupt source is level 7 and the application has interrupt sources mapped to level 7 and
3. If more than one interrupt source shares the same level, then check both sources.
4. If necessary, check for which of several possible conditions within a module caused the inter-
blrl
blr
lwz
lwz
mtxer
rfi
8. This value will be an index to a jump table.
beyond, then check the UIPEND register for levels beyond level 7. The CNTLZW instruction
can be used to count the number of zeros in the UIPEND from bit 0 until the first “1”. The number
can then be used as an index to a second jump table.
rupt. For example, which of 16 TPU channels caused the TPU interrupt.
Save the address of the next instruction to the LR by using the “l” option in the
branch instruction. For example:
Depending on the interrupt source, it may be necessary to negate the interrupt con-
dition so it will not cause further interrupts.
; Jump to interrupt handler routine and save the next instructions address in LR
; Return from interrupt handler routine to restore contexts.
r4, 40 (sp)
r3, 20 (sp)
r3
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For More Information On This Product,
Rev. 0, 26 July 2001
; Restore gpr4 from stack
; Restore XER value from stack
; Copy XER value to XER register
MPC555 Interrupts
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IMPORTANT
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