AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 17

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

3.6 Interrupt Sources: UIMB Peripherals
IMB peripherals needing faster interrupt response should use levels 0 through 6 since only SIVEC reg-
ister is necessary to identify the interrupt source, unless more than one source shares the same level.
IMB interrupt levels 7:31 are all “shared” on level 7 input to the USIU interrupt controller. Hence addi-
tional decoding of a source is normally required, which would use the UIPEND register.
The UIPEND register reflects the status of the 32 IMB interrupt levels. It is a read-only register.
The levels coming into the UIMB from the UIMB peripherals use multiplexing for efficiency. Levels in
these peripherals are represented by five bits [0:31]. The UIMB does not read all levels at once. It time
multiplexes a three-bit level value [0:7] with four time slots as shown in
The UMCR register contains the control bits called IRQMUX to enable mapping of 32 possible interrupt
requests from the UIPEND to the eight interrupt inputs of the USIU interrupt controller.
The UIMB interrupt sources include the following peripheral modules on the UIMB bus: two TouCAN
modules, two QADC modules, two TPU modules, one MIOS1 module, and one QSMCM module. Each
module has numerous conditions that can cause an interrupt, but have only one or two interrupt levels.
For example, any of a TPU’s 16 channels can be set up to cause an interrupt, but there is only one in-
terrupt line (level) leaving the module. (See
only that the TPU caused the interrupt, but which channel caused it as well.
Levels are assigned in the module’s level register. Although there are 32 possible levels, they are mul-
tiplexed on to eight inputs to the UIMB. For historical reasons, peripherals designate levels in two pos-
sible methods:
1. A single 5 bit “level” field, for levels 0 – 31 as follows. This applies to interrupt sources in USIU,
2. A 3-bit “level” field for levels 0:7 and a 2 bit “time multiplex” or “byte select” field for multiplexing
QADC, and QSMCM modules.
levels to a time slot. This applies to interrupt sources in TPU3 and MIOS1 modules.
Multiplexed 3-bit
0 … 7
0 … 7
0 … 7
0 … 7
Level
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 12 UIMB Interrupt Level Assigment
5-bit Level Field Value
Table 11 UIMB Time Multiplexing
Rev. 0, 26 July 2001
MPC555 Interrupts
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00000
00001
00010
11111
for 5-bit Level Field
2-bit Time Slot
—
Table
0
1
2
3
25.) The interrupt service routine must determine not
Level
31
—
0
1
2
Generated IRQ Level
16 … 23
24 … 31
8 … 15
0 … 7
Table
11.
MOTOROLA
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