AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 23

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

6.2 Step 2: Set MSR[RI]
6.3 Step 3: Save Other Appropriate Context (Registers)
6.4 Step 4: Determine Interrupt Source
2.
MPC555 Users Manual,
The following illustrates saving the machine context for a stack frame of size 80 bytes. Register r3 is
saved so it can be used as a scratch register. We will assume the assembler has the symbol “sp” de-
fined as “r1” for legibility. This illustration assumes what to save and where to save it on the stack frame
has been defined. Complete examples are provided
rupt Service
As described earlier, the recoverable interrupt bit in the machine state register indicates the machine
state can be recovered if a subsequent exception occurs. If SRR0 and SRR1 have been saved as in
step 1, software should set this bit to indicate to any other exception routine this backed up condition,
(i.e., recoverable state). This bit is most easily set writing any gpr to the special purpose register EID.
Example:
Any asynchronous exception (such as reset) could check the RI bit of the MSR now saved in the SRR1.
If the RI bit is 0, then the software will know the exception is non-recoverable. This can only happen if
there is a reset or some major problem with either the software or the whole system.
Debugging Comments: Since debugging is also done by exception, if a breakpoint is taken while RI =
0, then machine state is presumed lost. In general, breakpoints are recognized in the CPU only when
the RI bit is set, which guarantees that the machine restarts after a breakpoint.
points are considered “masked”. Internal breakpoints also have a non-masked mode where they are
recognized at any time. If one occurs while RI=0, then the user can debug the exception routine, how-
ever at the end of the exception there is no way to return to the main program.
Based on what else the user has determined to be saved on the stack, code will save appropriate reg-
isters. Any gpr registers can be saved with one instruction. For example:
Special-purpose registers take two instructions, like SRR0 and SRR1. Example:
To optimize saving and later restoring context, the load / store multiple word (lmw / stmw) or load / store
string word immediate (lswi / stswi) instructions can be used. Using the multiple word or string word im-
mediate instructions also shorten execution time. (The lmw / stmw instructions start saving registers at
r31, so this would be if all the gprs would be saved.)
If interrupt nesting is to be allowed, then the SIMASK register may also need to be saved and MSR[EE]
bit set. An example later illustrates how this is done.
To determine the interrupt source, the following sequence can be taken:
stwu
stw
mfsrr0
stw
mfsrr1
stw
mtspr
stw
mfxer
stw
sp, -80 (sp); Create stack frame and store back chain
r3, 36 (sp); Save a working register in stack frame for use as a scratch register
r3
r3, 12 (sp); Save SRR0 value on stack
r3
r3, 16 (sp); Save SRR1 value on stack
EID, r3; Set MSR[RI] to indicate recoverable condition
Routines.
r4, 40 (sp)
r3
r3, 20 (sp)
; Copy SRR0 to r3
; Copy SRR1 to r3
(MPC555UM/AD),
Freescale Semiconductor, Inc.
For More Information On This Product,
Rev. 0, 26 July 2001
; Store gpr4 on stack
; Copy special purpose register XER to gpr3
; Save XER value to stack
MPC555 Interrupts
Go to: www.freescale.com
21.3 Watchpoints and Breakpoints
Section 7 Examples of Initialization and Inter-
Support, Rev. 1 June 2000
2
In this mode, break-
MOTOROLA
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