AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 2

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

2.3 Exception Vector and Exception Vector Table
• Peripheral modules on the intermodule bus (IMB3): TPU3, QADC, QSMCM, MIOS, and TouCAN.
An interrupt level is a number which is assigned by software to all interrupt sources except input pins
IRQ[0:7]. This number, or level, provides a mapping mechanism for software to identify which interrupt
source is causing an interrupt request. Levels also imply a priority if two or more interrupt requests occur
at the same time (see
levels because they have fixed priorities.
An exception vector is an address where the processor begins execution after an exception is recog-
nized and the immediate state of the machine saved. (This differs from 68000 architecture where vec-
tors are pointers — PowerPC vectors have fixed locations.) Each exception has its own exception
vector, which is the sum of a base address and a vector offset:
The exception base address is commonly either 0x0 or 0xFFF0 0000, depending on if the MSR[IP]
bit. The base can have alternate values with exception vector “relocation” discussed later.
Each exception has its own exception vector offset. The normal offsets are shown in
An Exception Vector Table, sometimes just called exception table, is a table of exceptions and their
vectors. For example, if the exception base address = 0x0, then the table is simply the exception vector
offsets (as in the prior paragraph). If the exception base address is 0xFFF0 0000, then the exception
vector table is shown in
System Reset or Non-Maskable Interrupt
Machine Check
Reserved
Reserved
External Interrupts
etc.
System Reset or Non-Maskable Interrupt
Machine Check
Reserved
Reserved
External Interrupts
etc.
Table 8
Name of Exception
Name of Exception
Freescale Semiconductor, Inc.
Table
For More Information On This Product,
Table 1 Normal Exception Vector Offsets
Table 2 Example Exception Vector Table
+
2.
for priorities of input pins and levels). Interrupt pins do not get assigned
Rev. 0, 26 July 2001
Exception Base Address
Exception Vector Offset
----------------------------------
Exception Vector
MPC555 Interrupts
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Exception Vector
0xFFF0 0100
0xFFF0 0200
0xFFF0 0300
0xFFF0 0400
0xFFF0 0500
Offset
0x100
0x200
0x300
0x400
0x500
etc.
etc.
Table
MOTOROLA
1.
2