AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 16

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

Registers used
to enable ints
and read the
status. Level
setting regs.
are not
shown
NOTE: UIPEND levels 0:6 map directly to SIPEND levels 0:6. UIPEND 7:31 map to SIPEND level 7.
can be set to
Peripheral
Interrupts
Table 10
any level
TPU3_A
CIER
CISR
summarizes the mapping.
from IMB Peripheral to
[16]
Levels 0 -7
L0
Interrupt Level
UIMB Module
SIPEND Levels 0:6
TPU3_B
L1 L2 L3 L4 L5 L6
CIER
CISR
7:31
[16]
Figure 4 Peripherals and the UIMB Interrupt Structure
0
1
2
3
4
5
6
Freescale Semiconductor, Inc.
MIOS1ER0 or 1
MIOS1SR0 or 1
For More Information On This Product,
MIOS1
Table 10 UIMB Interrupt Level Mapping
[20]
Rev. 0, 26 July 2001
MPC555 Interrupts
UIMB Module to USIU
Levels 8-15
Interrupt Level from
L7
Interrupt Controller
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QADC64_A
Interrupt levels 8 to 31 are optionally enabled
QACR1
QACR2
QASR0
[4]
0
1
2
3
4
5
6
7
SIPEND Level 7
IMB3 BUS
QADC64_B
QACR1
QASR0
QACR2
Levels 16-23
[4]
Normal – use SIVEC and UIPEND
Relative Overhead to Identify
IFLAG
TOUCAN_A
CANCTRL0
TCNMCR
IMASK
Fast – use SIVEC only
Fast – use SIVEC only
Fast – use SIVEC only
Fast – use SIVEC only
Fast – use SIVEC only
Fast – use SIVEC only
Fast – use SIVEC only
IRQMUX0 IRQMUX1
Interrupt Source
ESTAT
[19]
use of levels 8-31
UMCR enables the
IFLAG
UIPEND
TOUCAN_B
CANCTRL0
TCNMCR
IMASK
UIPEND has 32 IMB3
interrupt levels that map
to SIPEND with the
external interrupts.
[19]
Levels 24-31
ESTAT
UIMB module
SPCR2 SPCR3
Interrupt levels are
time-multiplexed
SPSR
SPI
onto bus
QSMCM
MOTOROLA
UMCR
[15]
sources in []
interrupt
SCCxR1
SCxSR
No. of
SCI
16