AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 22

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

6 Interrupt Service Routine Steps
6.1 Step 1: Save “Machine Context”
A general interrupt sequence of events is summarized in
pose registers, a gpr must be saved also because it must be used as a scratch register for transfer pur-
poses. These are illustrated in
through
“Machine context” here means the save and restore registers, SRR0 and SRR1. These get loaded with
the machine state by the CPU when any exception (including debugger) is taken. Therefore if another
exception occurs without saving SRR0:1, the original machine state is lost. The expected normal prac-
tice is to save these on the stack. This step is not required if no other exceptions will occur during the
exception routine.
Since the PowerPC architecture does not allow direct writing of special-purpose registers directly to
memory, a general-purpose register must be used as an intermediary for storing these values. This
means the gpr used itself must also be saved on the stack.
The PowerPC architecture does not support any hardware stack, so software will manage it. By con-
vention (EABI), general-purpose register 1 (gpr1, or just “r1”) is used for a stack pointer.
Exception occurs
Currently executing instructions are
completed
The CPU saves the address of next
instruction and MSR[16:31] in
SRR0:1, then modifies MSR
(see
The instruction pointer branches to
the exception vector address.
The CPU restores return address,
original MSR, and enables interrupts
again.
Program execution resumes in the
routine that was interrupted.
Section 7.3.6 Example 6: ISR with Nested
3.1 PowerPC Core
System Behavior
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Interrupt).
Table 16 Interrupt Event Sequence
Rev. 0, 26 July 2001
MPC555 Interrupts
Section 7.3.2 Example 2: ISR Using Assembly Language Only
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1. Save “Machine Context” of SRR0:1.
2. Set MSR[RI] to indicate the state is now recoverable.
Other maskable interrupts/exceptions could now be
enabled.
3. Save other appropriate context (registers).
4. Determine interrupt source.
5. Branch to interrupt handler and execute it. If
necessary, negate the interrupt request in the handler.
6. Restore contexts, disabling maskable exceptions &
clearing MSR[RI] appropriately.
7. Return to program by executing “rfi” instruction.
Interrupts.
Table
Software Steps
16. When software saves special-pur-
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