AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 18

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

3.7 A Note on Interrupt Nesting
A common rule is to have each module use a different interrupt level to minimize interrupt service rou-
tine time in determining the source of the interrupt. The lower number levels have priority of higher num-
bers if two interrupts occur at the same time, so the more important interrupt sources must reside at
lower levels.
As shown in the tables of
have multiple interrupt sources sharing a level. The enable bits must be set for the desired interrupt
sources. When an interrupt condition is met, such as a communication buffer becoming empty, that con-
dition is “anded” with its enable bit to determine if an interrupt request gets passed on. The interrupt
service routine, once identifying the module causing an interrupt, checks the status bits for determining
the specific interrupt source causing the interrupt.
Once an interrupt has been recognized by the core, the hardware context switch disables further inter-
rupts. There are two options:
If the interrupt service routine is relatively short, no nesting is necessary. If nesting is used, additional
steps (overhead) are required.
If interrupt nesting is desired, it is accomplished by first setting the MSR[EE] again as soon as it is “safe”
to do so at the beginning of the interrupt service routine. Later the same EE bit must be cleared before
the final context switch at the end of the interrupt service routine. In addition, the SIMASK register must
be saved, lower priority interrupts masked in it, and SIMASK restored later. A conceptual example is
provided in
1. No interrupt nesting: Keep interrupts disabled during the entire interrupt service routine.
2. Interrupt nesting: Enable interrupts in a window inside the interrupt service routine.
Section 7.3.6 Example 6: ISR with Nested
3-bit Level Field Value
000 to 111
000 to 111
000 to 111
000 to 111
Freescale Semiconductor, Inc.
Section Appendix A Table of Potential Interrupt
For More Information On This Product,
Table 13 UMB Interrupt Level Assignment
Rev. 0, 26 July 2001
MPC555 Interrupts
for 3- and 2-bit Level FIelds
Go to: www.freescale.com
2-bit Time Multiplex or
Byte Select Field
00
01
10
11
Interrupts.
Peripheral Interrupt
16 to 23
24 to 31
8 to 15
Level
0 to 7
Sources, UIMB modules
MOTOROLA
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