AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 52

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

Appendix B Enhanced Interrupt Controller Summary
MPC5xx family after the MPC555 include an enhanced interrupt controller feature. This feature is found
on the MPC565 microprocessor as well as other MPC56x family members. A summary of differences
from the MPC555 interrupt controller is listed below.
Benefit: Significantly reduces software overhead of interrupt service routines.
New Features:
• Number of interrupt levels increased from eight to 40
• External Interrupt Relocation: Automatic decoding of interrupt source level or interrupt input pin for a
• Automatic masking of lower and same priority interrupt levels for nesting interrupts
Compatibility: The MPC555 interrupt controller, called “regular interrupt controller”, is still included and
is enabled by default out of reset.
General Steps to Activate External Interrupt Relocation
branch table
1. Program the external interrupt branch table base address in EIBADR
2. Insert branch absolute instructions (“ba”) for each interrupt in table
3. Set MSR[IP] bit
4. Set BBCMCR[EIR] to enable external interrupt relocation
5. Set SIUMCR[EICEN] to enable the enhanced interrupt controller
— Reduces or eliminates sharing of levels by peripherals
— Additional 32 levels are available for UIMB sources; USIU continues to use the regular 8 levels
— New Control Bit:
— New Registers:
— No decoding of SIVEC[Interrupt_Code] required; levels have own exception vector address
— Requires BBCMCR[ETRE = 1]
— New Control Bit:
— New Registers:
— No need to manipulate SIMASK register at start and end of interrupt service routine
— New Control Bit:
— New Registers:
• SIUMCR[EICEN], enhanced interrupt controller enabled
• SIPEND2, SIPEND3 — use instead of SIPEND
• SIMASK2, SIMASK3 — use instead of SIMASK
• BBCMCR[EIR], enhanced external interrupt relocation enabled
• EIBADR, external interrupt relocation table base address register
• SIUMCR[LPMASK_EN], low priority request masking enabled
• SISR2, SISR3 masks same and lower priority interrupts
Freescale Semiconductor, Inc.
For More Information On This Product,
Rev. 0, 26 July 2001
MPC555 Interrupts
Go to: www.freescale.com
MOTOROLA
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