AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 3

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

2.4 Exception Table Relocation
1.
addition, these parts can map the exception table to the internal RAM and to the second flash module (if present).
On future MPC5xx parts with larger flash blocks, this address will be 0x1 0000 (the second 64 Kbyte flash block). In
A feature in the MPC555 allows having tighter exception vector offsets for the purpose of saving mem-
ory space. This feature, called exception table relocation, “relocates” exception vector offsets by:
• “Relocating” exception vector offsets to be eight bytes apart, instead of 0x100 (256) bytes.
• Allowing additional exception vector base values of: 0x8000 (32 Kbytes)
To use the relocation feature, the control bits in
MSR[IP]
BBCMCR[ETRE]
BBCMCR[OERC]
IMMR[ISB]
A complete table of all possible exception vectors is listed in
base (ISB) is at 0x0.
NOTES:
with the mapping of the internal memory space base, as indicated in the internal memory mapping
register, IMMR[ISB] bit field.
1. On the MPC565 and other future members of the MPC5xx family the OERC field is two bits wide instead
Register[Bit]
of one and is located in different bit positions of the BBCMCR. Two bits allows for more possible excep-
tion locations. See the information below (assumes MSR[IP] = 1 and BBCMCR[ETRE] = 1).
MPC555
OERC
0
1
–
–
–
When using the relocation feature, a branch absolute (ba) instruction, not just a
branch (b) instruction, must be used at each relocated vector address. Otherwise
exceptions will not work.
MPC565
OERC0
0
–
0
1
1
1
Instruction Prefix
Exception Table Relocation Enable
Other Exception Relocation Enable
Internal Memory Space Base
Freescale Semiconductor, Inc.
For More Information On This Product,
OERC1
0
–
1
0
1
Table 3 Relocation Feature Control Bits
Rev. 0, 26 July 2001
MPC555 Interrupts
Go to: www.freescale.com
Bit Name
Exception Table Location
0x0 + ISB offset
0x8 000 + ISB offset
0x1 0000 + ISB offset
0x8 0000 + ISB offset
0x3F E000 + ISB offset
CAUTION
Table 3
are used.
Controls the main base address, either at
0x0 or 0xFFF0 0000.
Enables exception vector addresses
relocation. Addresses are separated by 8
bytes instead of 256 bytes. (Requires
MSR[IP] = 1.)
Provides an additional offset to the base
address when relocation is used.
Moves exception table base with internal
memory space. (Requires MSR[IP] = 1 and
BBCMCR[ETRE] = 1.)
Table 4
when the internal memory space
Description
1
and/or bases which move
MOTOROLA
3