ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 100

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 to 0: T4 DPLL Bandwidth (T4BW[2:0]). See Section 7.7.3.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Reserved Bit 1 (RSV1). This bit is reserved for future use, it can be written to and read back.
Bits 3 to 0: T0 DPLL Locked Bandwidth (T0LBW[3:0]). This field configures the bandwidth of the T0 DPLL when
locked to an input clock. When AUTOBW = 0 in the
and for locked operation. When AUTOBW = 1,
is used for locked operation. See Section 7.7.3.
________________________________________________________________________________________ DS3104-SE
000 = 18Hz
001 = 35Hz
010 = 70Hz
011 = {unused value, undefined}
1000 = 0.1Hz
1001 = 0.3Hz
1010 = 0.6Hz
1011 = 1.2Hz
1100 = 2.5Hz
1101 = 4Hz (default)
1110 = 8Hz
1111 = 18Hz
0000 = 35Hz
0001 = 70Hz
0010 = {unused values, undefined}
0011 = 18Hz
0100 = 120Hz
0101 = 250Hz
0110 = 400Hz
0111 = 18Hz
Bit 7
Bit 7
—
0
0
0
Bit 6
Bit 6
—
0
0
0
T4BW
T4 Bandwidth Register
66h
T0LBW
T0 DPLL Locked Bandwidth Register
67h
Bit 5
Bit 5
—
0
0
0
T0ABW
MCR9
RSV1
Bit 4
Bit 4
0
0
0
bandwidth is used for acquisition while T0LBW bandwidth
register, the T0LBW bandwidth is used for acquisition
Bit 3
Bit 3
0
0
1
Bit 2
Bit 2
0
0
1
T0LBW[3:0]
Bit 1
Bit 1
0
0
T4BW[1:0]
Bit 0
Bit 0
0
1
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