ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 25

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.7
Both T0 and T4 are digital PLLs with separate analog PLLs (APLLs) as the output stage. This architecture
combines the benefits of both PLL types. See
Figure 7-1. DPLL Block Diagram
Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations,
temperature, and voltage; and (2) flexible behavior that is easily programmed via configuration registers. DPLLs
use digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8MHz) is
multiplied up from the 12.800MHz local oscillator clock applied to the REFCLK pin. This master clock is then
digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1ns pk-pk.
________________________________________________________________________________________ DS3104-SE
T0 selected
T4 selected
reference
reference
SYNC2K
DPLL Architecture and Configurat ion
Frequency
Locking
Loop Filter
Loop Filter
PFD and
PFD and
Frequency
Locking
SYNC2K
T0CR1:T4MT0
T4
T0
T4 DPLL
T0 DPLL
0
1
ICRn:FREQ[3:0]
Feedback
ICRn:FREQ[3:0]
Feedback
Foward
Foward
DFS
DFS
T0
T0
DFS
DFS
T4
T4
Figure
MCR7:DIG1SRC
MCR7:DIG2SRC
T0CR1:T4APT0
T0CR1:LKT4T0
FSCR1:2K8KSRC
T0CR1:LKT4T0
T0CR1:LKT4T0
T0CR1:LKT4T0
OUTPUT DFS
7-1.
T0CR1:T0FREQ[2:0]
T4CR1:T4FREQ[3:0]
T0CR1:T0FT4[2:0]
MCR6:DIG1F[1:0]
MCR6:DIG2F[1:0]
FSYNC
APLL2
DIG12
MCR6:DIG1SS
DIG12
MCR6:DIG2SS
MCR6:DIG2AF
APLL
APLL
2K8K
DFS
DFS
DFS
DFS
DFS
DFS
DFS
T4
T0
T0
2
FSCR2:INDEP
Output
Output
Output
PLL Bypass
APLL2
APLL
APLL
T4
T0
T0
2K8K
DIG1
DIG2
2
Dividers
Dividers
Dividers
Output
Output
Output
APLL
APLL
APLL
FSCR1:8KPOL, 2KPOL
FSCR1:8KINV, 2KINV
OCR4:FSEN, MFSEN
OCRm:OFREQn[3:0]
OCR5:AOFn
OC1, OC2,
OC3, OC4,
OC5, OC6,
OC7
FSYNC,
MFSYNC
25