ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 78

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ds3104-se

Manufacturer Part Number
ds3104-se
Description
Line Card Timing Ic With Synchronous Ethernet Support
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies.
Bit 6: Digital2 SONET or SDH Frequencies (DIG2SS). This bit specifies whether the clock rates generated by the
Digital2 clock synthesizer are multiples of 1.544MHz (SONET-compatible) or multiples of 2.048MHz (SDH-
compatible) or alternate frequencies. The specific multiple is set in the DIG2F field of the
RST = 0 the default value of this bit is latched from the SONSDH pin.
Bit 5: Digital1 SONET or SDH Frequencies (DIG1SS). This bit specifies whether the clock rates generated by the
Digital1 clock synthesizer are multiples of 1544kHz (SONET compatible) or multiples of 2048kHz (SDH
compatible). The specific multiple is set in the DIG1F field of the
this bit is latched from the SONSDH pin.
________________________________________________________________________________________ DS3104-SE
0 = Digital2 NxE1 or NxDS1 frequency specified by DIG2SS and MCR7:DIG2F.
1 = Digital2 6.312MHz, 10MHz, or Nx19.44MHz frequency specified by DIG2SS and MCR7:DIG2F.
DIG2AF = 0:
DIG2AF = 1:
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
6.312MHz, 10 MHz or Nx19.44MHz
DIG2AF
Bit 7
0
see below
DIG2SS
Bit 6
MCR6
Master Configuration Register 6
38h
see below
DIG1SS
Bit 5
Bit 4
1
MCR7
Bit 3
1
register. When RST = 0 the default value of
Bit 2
1
MCR7
Bit 1
1
register. When
Bit 0
1
78

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