ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 89

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Leaky Bucket 0 Upper Threshold (LB0U[7:0]). When the leaky bucket accumulator is equal to the
value stored in this field, the activity monitor declares an activity alarm by setting the input clock’s ACT bit in the
appropriate
See Section 7.5.2.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Leaky Bucket 0 Lower Threshold (LB0L[7:0]). When the leaky bucket accumulator is equal to the
value stored in this field, the activity monitoring logic clears the activity alarm (if previously declared) by clearing the
input clock’s ACT bit in the appropriate
leaky bucket configuration 0. See Section 7.5.2.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Leaky Bucket 0 Size (LB0S[7:0]). This field specifies the maximum value of the leaky bucket. The
accumulator cannot increment past this value. Registers LB0U, LB0L, LB0S, and
bucket configuration 0. See Section 7.5.2.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 1 to 0: Leaky Bucket 0 Decay Rate (LB0D[1:0]). This field specifies the decay or “leak” rate of the leaky
bucket accumulator. For each period of 1, 2, 4, or 8 128ms intervals in which no irregularities are detected on the
input clock, the accumulator decrements by 1. Registers LB0U, LB0L, LB0S, and
bucket configuration 0. See Section 7.5.2.
________________________________________________________________________________________ DS3104-SE
00 = decrement every 128ms (8 units/second)
01 = decrement every 256ms (4 units/second)
10 = decrement every 512ms (2 units/second)
11 = decrement every 1024ms (1 unit/second)
ISR
Bit 7
Bit 7
Bit 7
Bit 7
register. Registers LB0U, LB0L,
—
0
0
0
0
Bit 6
Bit 6
Bit 6
Bit 6
—
0
0
0
0
LB0U
Leaky Bucket 0 Upper Threshold Register
50h
LB0L
Leaky Bucket 0 Lower Threshold Register
51h
LB0S
Leaky Bucket 0 Size Register
52h
LB0D
Leaky Bucket 0 Decay Rate Register
53h
ISR
Bit 5
Bit 5
Bit 5
Bit 5
—
0
0
0
0
register. Registers LB0U, LB0L, LB0S, and
LB0S
Bit 4
Bit 4
Bit 4
Bit 4
—
0
0
0
0
and
LB0U[7:0]
LB0S[7:0]
LB0L[7:0]
LB0D
Bit 3
Bit 3
Bit 3
Bit 3
together specify leaky bucket configuration 0.
—
0
0
1
0
Bit 2
Bit 2
Bit 2
Bit 2
—
1
1
0
0
LB0D
LB0D
LB0D
together specify leaky
together specify leaky
Bit 1
Bit 1
Bit 1
Bit 1
1
0
0
0
LB0D[1:0]
together specify
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
1
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