ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 26

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

The analog PLLs filter the jitter from the DPLLs, reducing the 1ns pk-pk jitter to less than 0.5ns pk-pk and 60ps
RMS, typical, measured broadband (10Hz to 1GHz).
The DPLLs in the device are configurable for many PLL parameters including bandwidth, damping factor, input
frequency, pull-in/hold-in range, input-to-output phase offset, phase build-out, and more. No knowledge of loop
equations or gain parameters is required to configure and operate the device. No external components are
required for the DPLLs or the APLLs except the high-quality local oscillator connected to the REFCLK pin.
The T0 DPLL to T0 APLL path is the main path through the device. The T0 DPLL has a full free-
run/locked/holdover state machine and full programmability. The T4 DPLL to T4 APLL path is a simpler frequency
converter/synthesis path, lacking the low bandwidth settings, phase build-out, and phase adjustment controls found
in the T0 DPLL.
7.7.1 T0 DPLL State Machine
The T0 DPLL has three main timing modes: locked, holdover and free-run. The control state machine for the T0
DPLL has states for each timing mode as well as three temporary states: prelocked, prelocked 2 and loss-of-lock.
The state transition diagram is shown in
During normal operation the state machine controls state transitions. When necessary, however, the state can be
forced using the T0STATE field of the
Whenever the T0 DPLL changes state, the STATE bit in
enabled. The current T0 DPLL state can be read from the T0STATE field of the
7.7.1.1 Free-Run State
Free-run mode is the reset default state. In free-run all output clocks are derived from the 12.800 MHz local
oscillator attached to the REFCLK pin. The frequency of each output clock is a specific multiple of the local
oscillator. The frequency accuracy of each output clock is equal to the frequency accuracy of the master clock,
which can be calibrated using the MCLKFREQ field in registers
machine transitions from free-run to the prelocked state when at least one input clock is valid.
7.7.1.2 Prelocked State
The prelocked state provides a 100-second period (default value of
selected reference. If phase lock (see Section 7.7.6) is achieved for 2 seconds during this period then the state
machine transitions to locked mode.
If the DPLL fails to lock to the selected reference within the phase-lock timeout period specified by
phase lock alarm is raised (corresponding LOCK bit set in the
in
lock to the alternate input clock. If no other input clocks are valid for two seconds, then the state machine
transitions back to the free-run state.
In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock
timeout period then the state machine re-enters the prelocked state and tries to lock the higher priority input.
If a phase-lock timeout period longer than 100 seconds is required for locking, then the
configured accordingly.
________________________________________________________________________________________ DS3104-SE
VALSR
registers). If another input clock is valid then the state machine re-enters the prelocked state and tries to
MCR1
Figure
register.
7-2. Descriptions of each state are given in the paragraphs below.
MSR2
ISR
MCLK1
is set, which can cause an interrupt request if
register), invalidating the input (ICn bit goes low
PHLKTO
and
MCLK2
register) for the DPLL to lock to the
OPSTATE
(see Section 7.3). The state
PHLKTO
register.
register must be
PHLKTO
then a
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