ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 24

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

________________________________________________________________________________________ DS3104-SE
in revertive mode, ultra-fast switching could cause excessive reference switching when the highest priority input is
intermittent.
7.6.5 External Reference Switching Mode
In this mode the SRCSW input pin controls reference switching between two clock inputs. This mode is enabled by
setting the EXTSW bit to 1 in the
MCR10
register. In this mode, if the SRCSW pin is high, the T0 DPLL is forced to
lock to input IC3 (if the priority of IC3 is nonzero in IPR2) or IC5 (if the priority of IC3 is zero) whether or not the
selected input has a valid reference signal. If the SRCSW pin is low the T0 DPLL is forced to lock to input IC4 (if
the priority of IC4 is nonzero in IPR2) or IC6 (if the priority of IC4 is zero) whether or not the selected input has a
valid reference signal. During reset the default value of the EXTSW bit is latched from the SRCSW pin. If external
reference switching mode is enabled during reset, the default frequency tolerance
(DLIMIT
registers) is configured
to r80ppm rather than the normal default of r9.2ppm.
In external reference switching mode the device is simply a clock switch, and the T0 DPLL is forced to lock onto the
selected reference whether it is valid or not. Unlike forced reference selection (Section 7.6.3) this mode controls the
PTAB1:SELREF field directly and is, therefore, not affected by the state of the MCR3:REVERT bit. During external
reference switching mode, only PTAB1:SELREF is affected; the REF1, REF2, and REF3 fields in the
PTAB
registers continue to indicate the highest, second-highest, and third-highest priority valid inputs chosen by the
automatic selection logic. External reference switching mode only affects the T0 DPLL.
7.6.6 Output Clock Phase Continuity During Reference Switching
If phase build-out is enabled (PBOEN = 1 in MCR10) or the DPLL frequency limit (DLIMIT) is set to less than
r30ppm, the device always complies with the GR-1244-CORE requirement that the rate of phase change must be
less than 81ns per 1.326ms during reference switching.
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