ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 109

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified in the
COARSELIM[3:0] field. This field controls both T0 and T4. See Section 7.7.6.
Bit 6: Multicycle Phase Detector Enable (MCPDEN). This configuration bit enables the multicycle phase detector
and allows the DPLL to tolerate large-amplitude jitter and wander. The range of this phase detector is the same as
the coarse phase limit specified in the COARSELIM[3:0] field. This field controls both T0 and T4. See Section
7.7.5.
Bit 5: Use Multicycle Phase Detector in the DPLL Algorithm (USEMCPD). This configuration bit enables the
DPLL algorithm to use the multicycle phase detector so that a large phase measurement drives faster DPLL pull-in.
When USEMCPD = 0, phase measurement is limited to r360q, giving slower pull-in at higher frequencies but with
less overshoot. When USEMCPD = 1, phase measurement is set as specified in the COARSELIM[3:0] field, giving
faster pull-in. MCPDEN should be set to 1 when USEMCPD = 1. This field controls both T0 and T4. See Section
7.7.5.
Bits 3 to 0: Coarse Phase Limit (COARSELIM[3:0]). This field specifies the coarse phase limit and the tracking
range of the multicycle phase detector. The CLEN bit enables this feature. If jitter tolerance greater than 0.5UI is
required and the input clock is a high frequency signal then the DPLL can be configured to track phase errors over
many UI using the multicycle phase detector. This field controls both T0 and T4. See Section
________________________________________________________________________________________ DS3104-SE
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0000 = r1UI
0001 = r3UI
0010 = r7UI
0011 = r15UI
0100 = r31UI
0101 = r63UI
0110 = r127UI
0111 = r255UI
1000 = r511UI
1001 = r1023UI
1010 = r2047UI
1011 = r4095UI
1100 to 1111 = r8191UI
CLEN
Bit 7
1
MCPDEN
Bit 6
0
PHLIM2
Phase Limit Register 2
74h
USEMCPD
Bit 5
0
Bit 4
—
0
Bit 3
0
Bit 2
COARSELIM[3:0]
1
7.7.5
Bit 1
0
and 7.7.6.
Bit 0
1
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