ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 67

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Holdover Frequency Ready (HORDY). This latched status bit is set to 1 when the T0 DPLL has a holdover
value that has been averaged over the 1-second holdover averaging period. HORDY is cleared when written with a
1. When HORDY is set it can cause an interrupt request on the INTREQ pin if the HORDY interrupt enable bit is
set in the
Bit 5: Multiregister Access Aborted (MRAA). This latched status bit is set to 1 when a multibyte access (read or
write) is interrupted by another access to the device. MRAA is cleared when written with a 1. MRAA cannot cause
an interrupt to occur. See Section 8.3.
________________________________________________________________________________________ DS3104-SE
IER4
register. See Section 7.7.1.6.
Bit 7
—
0
HORDY
Bit 6
0
MSR4
Master Status Register 4
17h
MRAA
Bit 5
0
Bit 4
—
0
Bit 3
—
0
Bit 2
—
0
Bit 1
—
0
Bit 0
—
0
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