ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 15

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Table 6-3. Global Pin Descriptions
Table 6-4. SPI Bus Mode Pin Descriptions
See Section
________________________________________________________________________________________ DS3104-SE
INTREQ/LOS
PIN NAME
PIN NAME
SONSDH/
SRCSW
SRFAIL
GPIO4
CPHA
LOCK
CPOL
TEST
SCLK
WDT
SDO
RST
SDI
CS
7.10
(1)
(1)
for functional description and Section
TYPE
TYPE
I/O
I
I
I
I/O
O
I
I
O
O
O
PU
PD
PD
PU
PD
I
I
I
PD
3
(2)
(2)
SRFAIL Status. When MCR10:SRFPIN = 1, this pin follows the state of the SRFAIL latched
status bit in the
current reference. When MCR10:SRFPIN = 0, SRFAIL is disabled (low).
Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is
reset to default values. The device is held in reset as long as RST is low. RST should be held
low for at least two REFCLK cycles after the external oscillator has stabilized and is providing
valid clock signals.
Source Switching. Fast source-switching control input. See Section 7.6.5. The value of this pin
is latched into MCR10:EXTSW when RST goes high. After RST goes high this pin can be used
to select between IC3/IC5 and IC4/IC6, if enabled.
Factory Test Mode Select. Wire this pin to V
Watchdog Timer Pin. Analog node for the REFCLK watchdog timer. Connect to a resistor (R)
to V
Section 7.3.
SONET/SDH Frequency Select Input or GPIO4 Pin. When RST goes high the state of this pin
sets the reset-default state of MCR3:SONSDH, MCR6:DIG1SS and MCR6:DIG2SS. After RST
goes high this pin can be used as a general-purpose I/O pin. GPCR:GPIO4D configures this
pin as an input or an output. GPCR:GPIO4O specifies the output value. GPSR:GPIO4 indicates
the state of the pin.
Reset latched values:
T0 DPLL LOCK Status. When MCR1.LOCKPIN = 1, this pin indicates the lock state of the T0
DPLL. When MCR1.LOCKPIN = 0, LOCK is disabled (low).
Interrupt Request/Loss of Signal. Programmable (default: INTREQ). The INTCR:LOS bit
determines whether the pin is indicates interrupt requests or loss of signal (i.e. loss of selected
reference).
INTCR:LOS = 0: INTREQ mode
INTCR:LOS = 1: LOS mode
Chip Select. This pin must be asserted (low) to read or write internal registers.
Serial Clock. SCLK is always driven by the SPI bus master.
Serial Data Input. The SPI bus master transmits data to the device on this pin.
Serial Data Output. The device transmits data to the SPI bus master on this pin.
Clock Phase. See
0 = Data is latched on the leading edge of the SCLK pulse.
1 = Data is latched on the trailing edge of the SCLK pulse.
Clock Polarity. See
0 = SCLK is normally low and pulses high during bus transactions.
1 = SCLK is normally high and pulses low during bus transactions.
DDIO
This pin indicates the real-time state of the selected reference activity monitor (see Section
7.5.3). This function is most useful when external switching mode (Section 7.6.5) is enabled
(MCR10:EXTSW = 1).
0 = SDH rates (N x 2.048MHz)
1 = SONET rates (N x 1.544MHz)
0 = Not Locked
1 = Locked
The behavior of this pin is configured in the
active low. Drive action can be push-pull or open drain. The pin can also be configured as
a general-purpose output if the interrupt request function is not needed.
and a capacitor (C) to ground. Suggested values are R = 20k: and C = 0.01PF. See
MSR2
10.4
Figure
Figure
register. This gives the system a very fast indication of the failure of the
for timing specifications.
7-5.
7-5.
PIN DESCRIPTION
PIN DESCRIPTION
SS
INTCR
for normal operation.
register. Polarity can be active high or
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