ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 5

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

________________________________________________________________________________________ DS3104-SE
List of Tables
Table 1-1. Applicable Telecom Standards................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 14
Table 6-3. Global Pin Descriptions ............................................................................................................................ 15
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 15
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 16
Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 16
Table 7-1. Input Clock Capabilities ............................................................................................................................ 19
Table 7-2. Locking Frequency Modes ....................................................................................................................... 20
Table 7-3. Default Input Clock Priorities .................................................................................................................... 22
Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 31
Table 7-5. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 35
Table 7-6. Output Clock Capabilities ......................................................................................................................... 37
Table 7-7. Digital1 Frequencies................................................................................................................................. 39
Table 7-8. Digital2 Frequencies................................................................................................................................. 39
Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 40
Table 7-10. T0 APLL Frequency Configuration ......................................................................................................... 40
Table 7-11. T0 APLL2 Frequency Configuration ....................................................................................................... 40
Table 7-12. T4 APLL Frequency Configuration ......................................................................................................... 41
Table 7-13. OC1–OC7 Output Frequency Selection ................................................................................................. 41
Table 7-14. Standard Frequencies for Programmable Outputs ................................................................................ 42
Table 7-15. External Frame Sync Source ................................................................................................................. 47
Table 8-1. Register Map ............................................................................................................................................ 53
Table 9-1. JTAG Instruction Codes ......................................................................................................................... 119
Table 9-2. JTAG ID Code ........................................................................................................................................ 120
Table 10-1. Recommended DC Operating Conditions ............................................................................................ 121
Table 10-2. DC Characteristics................................................................................................................................ 121
Table 10-3. CMOS/TTL Pins ................................................................................................................................... 122
Table 10-4. LVDS/LVPECL Input Pins .................................................................................................................... 122
Table 10-5. LVDS Output Pins ................................................................................................................................ 122
Table 10-6. LVPECL Level-Compatible Output Pins............................................................................................... 123
Table 10-7. Input Clock Timing................................................................................................................................ 125
Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 125
Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode............................................................ 125
Table 10-10. SPI Interface Timing ........................................................................................................................... 126
Table 10-11. JTAG Interface Timing........................................................................................................................ 128
Table 10-12. Reset Pin Timing ................................................................................................................................ 129
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 130
Table 12-1. CSBGA Package Thermal Properties, Natural Convection ................................................................. 132
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