ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 28

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

________________________________________________________________________________________ DS3104-SE
7.7.1.3 Locked State
The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states
when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.6). In the locked state
the output clocks track the phase and frequency of the selected reference.
If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the locked state.
While in the locked state, if the selected reference is so impaired that an activity alarm is raised (corresponding
ACT bit set in the
ISR
register), then the selected reference is invalidated (ICn bit goes low in
VALSR
registers),
and the state machine immediately transitions to either the prelocked 2 state (if another valid input clock is
available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).
If loss-of-lock (see Section 7.7.6) is declared while in the locked state then the state machine transitions to the loss-
of-lock state.
7.7.1.4 Loss-of-Lock State
When the loss-of-lock detectors (see Section 7.7.6) indicate loss of phase lock, the state machine immediately
transitions from the locked state to the loss-of-lock state. In the loss-of-lock state the DPLL tries for 100 seconds
(default value of
PHLKTO
register) to regain phase lock. If phase lock is regained during that period for more than
2 seconds, the state machine transitions back to the locked state.
If, during the phase-lock timeout period specified by PHLKTO, the selected reference is so impaired that an activity
alarm is raised (corresponding ACT bit set in the
ISR
registers), then the selected reference is invalidated (ICn bit
goes low in
VALSR
registers), and after being invalid for 2 seconds the state machine transitions to either the
prelocked 2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid).
If phase lock cannot be regained by the end of the phase-lock timeout period then a phase lock alarm is raised
(corresponding LOCK bit set in the
ISR
registers), the selected reference is invalidated (ICn bit goes low in
VALSR
registers), and the state machine transitions to either the prelocked 2 state (if another valid input clock is available)
or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).
7.7.1.5 Prelocked 2 State
The prelocked and prelocked 2 states are similar. The prelocked 2 state provides a 100-second period (default
value of
PHLKTO
register) for the DPLL to lock to the new selected reference. If phase lock (see Section 7.7.6) is
achieved for more than 2 seconds during this period then the state machine transitions to locked mode.
If the DPLL fails to lock to the new selected reference within the phase-lock timeout period specified by
PHLKTO
then a phase lock alarm is raised (corresponding LOCK bit set in the
ISR
registers), invalidating the input (ICn bit
goes low in
VALSR
registers). If another input clock is valid then the state machine re-enters the prelocked 2 state
and tries to lock to the alternate input clock. If no other input clocks are valid for 2 seconds, the state machine
transitions to the holdover state.
In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock
timeout period then the state machine re-enters the prelocked 2 state and tries to lock to the higher priority input.
If a phase-lock timeout period longer than 100 seconds is required for locking, then the
PHLKTO
register must be
configured accordingly.
7.7.1.6 Holdover State
The device reaches the holdover state when it declares its selected reference invalid for 2 seconds and has no
other valid input clocks available. During holdover the T0 DPLL is not phase locked to any input clock but instead
generates its output frequency from stored frequency information acquired while it was in the locked state. When at
least one input clock has been declared valid the state machine immediately transitions from holdover to the
prelocked 2 state and tries to lock to the highest priority valid clock.
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