ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 113

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Independent Frame Sync and Multiframe Sync (INDEP). When this bit is set to 0, the 8kHz frame sync on
FSYNC and the 2kHz multiframe sync on MFSYNC are aligned with the other output clocks when synchronized
with the SYNCn input. When this bit is 1, the frame sync and multiframe sync are independent of the other output
clocks, and their edge position may change without disturbing the other output clocks. See Section 7.9.5.
Bit 6: Sync OC-N Rates (OCN). See Section 7.9.2.
Bits 5 to 4: External Sync Sampling Phase 3 (PHASE3[1:0]). This field adjusts the sampling of the SYNC3 input
pin. Normally the falling edge of SYNC3 is aligned with the falling edge of the selected reference. All UI numbers
listed below are UI of the sampling clock. See Section 7.9.1.
Bits 3 to 2: External Sync Sampling Phase 2 (PHASE2[1:0]). This field adjusts the sampling of the SYNC2 input
pin. Normally the falling edge of SYNC2 is aligned with the falling edge of the selected reference. All UI numbers
listed below are UI of the sampling clock. See Section 7.9.1.
Bits 1 to 0: External Sync Sampling Phase 1 (PHASE1[1:0]). This field adjusts the sampling of the SYNC1 input
pin. Normally the falling edge of SYNC1 is aligned with the falling edge of the selected reference. All UI numbers
listed below are UI of the sampling clock. See Section 7.9.1.
________________________________________________________________________________________ DS3104-SE
0 = FSYNC and MFSYNC are aligned with other output clocks; all are synchronized by the SYNCn input
1 = FSYNC and MFSYNC are independent of the other clock outputs; only FSYNC and MFSYNC are
0 = SYNCn is sampled with a 6.48MHz resolution; the selected reference must be 6.48MHz
1 = If the selected reference is 19.44MHz, SYNCn is sampled at 19.44MHz and output alignment is to
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
synchronized by the SYNCn input
19.44MHz. If the selected reference is 38.88MHz, SYNCn is sampled at 38.88MHz. The selected
reference must be either 19.44MHz or 38.88MHz
INDEP
Bit 7
0
Bit 6
OCN
0
FSCR2
Frame Sync Configuration Register 2
7Bh
Bit 5
0
PHASE3[1:0]
Bit 4
0
Bit 3
0
PHASE2[1:0]
Bit 2
0
Bit 1
0
PHASE1[1:0]
Bit 0
0
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