ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 111

• Manufacturer Part Number: ics1893cy-10
• Description: 3.3-v 10base-t/100base-tx Integrated Phyceiver
• Manufacturer: Integrated Device Technology

ICS1893CY-10 Rev 1/07
Table 8-6. MAC/Repeater Interface Pins: 100M Symbol Interface (Continued)
RXD0
RXD1
RXD2
RXD3
RXDV
RXER
RXTRI
TXCLK
TXD0
TXD1
TXD2
TXD3
TXEN
TXER
MII Pin
Name
ICS1893CY-10 - Release
SRD0
SRD1
SRD2
SRD3
–
SRD4
STCLK
STD0
STD1
STD2
STD3
–
STD4
Symbol
Name
100M
Pin
No.
Pin
35
34
33
32
36
39
41
43
45
46
47
48
44
42
Copyright © 2007, Integrated Device Technology, Inc.
Connect
Connect
Output
Output
Output
Type
Input
Input
Input
Pin
No
No
Symbol Receive Data 0–3.
In 100M Symbol mode:
Receive Data Valid.
For the 100M Symbol Interface, this pin is a no connect. For
more information, see
Symbol Receive Data 4.
Receive (Interface), Tri-State.
This pin’s input is from a MAC. When this pin’s signal is logic:
Symbol Transmit Clock.
This pin’s description is the same as that given in
Symbol Transmit Data 0–3.
In 100M Symbol mode:
Transmit Enable.
For the 100M Symbol Interface, this pin is a no connect. For
more information, see
Symbol Transmit Data 4.
This pin’s description is the same as that given in
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Note: In 100M Symbol mode, TXEN is not used because the
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The ICS1893CY-10’s SRD0 pin transmits the
least-significant bit and the SRD4 pin transmits the
most-significant bit of the symbol received from its
MAC/Repeater interface.
The ICS1893CY-10 continually transfers the data it receives
from its MDI to its SRD[4:0] pins (that is, to its MAC/Repeater
Interface). In the 100M Symbol mode, data is not framed.
Therefore, the ICS1893CY-10 does not assert its RXDV
signal.
The ICS1893CY-10 transfers its receive data to the SRD[4:0]
pins synchronously on the rising edges of its SRCLK signal.
Low, the MAC indicates it is not in a tri-state condition.
High, the MAC indicates it is in a tri-state condition. In this
case, the ICS1893CY-10 acts to ensure that only one PHY is
active at a time. (A PHY address of 00 also tri-states the MII
interface.)
The ICS1893CY-10 STD0 pin receives the least-significant
bit and the STD4 pin receives the most-significant bit of the
symbol received from the MAC/Repeater interface.
The signals on the ICS1893CY-10 STD[4:0] pins are
continually and synchronously sampled on the rising edges
of its STCLK. These signals are independent of the TXEN
signal.
111
MAC/Repeater is responsible for sending both IDLE
symbols and data.
Chapter 8 Pin Diagram, Listings, and Descriptions
Table
Table
Pin Description
5-1.
5-1.
Table
Table
8-5.
8-5.