ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 97

• Manufacturer Part Number: ics1893cy-10
• Description: 3.3-v 10base-t/100base-tx Integrated Phyceiver
• Manufacturer: Integrated Device Technology

7.14.6 Twisted Pair Tri-State Enable, TPTRI (bit 19.7)
7.14.7 ICS Reserved (bits 19.6:1)
7.14.8 Automatic 100Base-TX Power-Down (bit 19.0)
ICS1893CY-10 Rev 1/07
Table 7-22. AMDIX_EN (Pin 10) and Control Bits 19. 9:8
The ICS1893CY-10 provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN
signals to a high-impedance state. When this bit is set to logic:
•
•
See
The Automatic 100Base-TX Power Down bit provides an STA with the means of enabling the
ICS1893CY-10 to automatically shut down 100Base-TX support functions when 10Base-T operations are
being used. When this bit is set to logic:
•
•
Note:
Default Values:
Definitions:
Zero, the Twisted Pair Interface is operational.
One, the Twisted Pair Interface is tri-stated.
Zero, the 100Base-TX Transceiver does not power down automatically in 100Base-TX mode.
One, and the ICS1893CY-10 is operating in 10Base-T mode, the 100Base-TX Transceiver automatically
turns off to reduce the overall power consumption of the ICS1893CY-10.
ICS1893CY-10 - Release
Section 7.11.2, “ICS Reserved (bits
straight transmit = TP_AP & TP_AN
cross
AMDIX_EN (Pin 3) AMDIX enable pin with 50 kOhm pull-up resistor
AMDIX_EN [19:9]
MDI_MODE [19:8] MDIO register 13h bit 8
AMDIX_EN
There are other means of powering down the 100Base-TX Transceiver (for example, when the
entire device is isolated using bit 0:10).
(Pin 3)
1
1
receive = TP_BP & TP_BN
transmit = TP_BP & TP_BN
receive = TP_AP & TP_AN
MDIO register 13h bit 9
Copyright © 2007, Integrated Device Technology, Inc.
AMDIX_EN
[Reg 19:9]
1
1
16.14:11)”, the text for which also applies here.
All rights reserved.
97
MDI_MODE
[Reg 19:8]
0
x
Chapter 7 Management Register Set
straight / cross (auto
selected)
straight / cross (auto
selected)
Configuration
Tx/Rx MDI