ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 79
ics1893cy-10
Manufacturer Part Number
ics1893cy-10
Description
3.3-v 10base-t/100base-tx Integrated Phyceiver
Manufacturer
Integrated Device Technology
Datasheet
1.ICS1893CY-10.pdf
(143 pages)
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7.8.2 Parallel Detection Fault (bit 6.4)
7.8.3 Link Partner Next Page Able (bit 6.3)
7.8.4 Next Page Able (bit 6.2)
7.8.5 Page Received (bit 6.1)
7.8.6 Link Partner Auto-Negotiation Able (bit 6.0)
ICS1893CY-10 Rev 1/07
The ICS1893CY-10 sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection
fault occurs when the ICS1893CY-10 cannot disseminate the technology being used by its remote link
partner.
Bit 6.4 is a latching high (LH) status bit. (For more information on latching high and latching low bits, see
Section 7.1.4.1, “Latching High Bits”
Bit 6.3 is a status bit that reports the capabilities of the remote link partner to support the Next Page
features of the auto-negotiation process. The ICS1893CY-10 sets this bit to a logic one if the remote link
partner sets the Next Page bit in its Link Control Word.
Bit 6.2 is a status bit that reports the capabilities of the ICS1893CY-10 to support the Next Page features of
the auto-negotiation process. The ICS1893CY-10 sets this bit to a logic one to indicate that it can support
these features.
The ICS1893CY-10 sets its Page Received bit to a logic one whenever a new Link Control Word is received
and stored in its Auto-Negotiation link partner ability register. The Page Received bit is cleared to logic zero
on a read of the Auto-Negotiation Expansion Register.
Bit 6.1 is a latching high (LH) status bit. (For more information on latching high and latching low bits, see
Section 7.1.4.1, “Latching High Bits”
If the ICS1893CY-10:
•
•
Does not receive Fast Link Pulse bursts from its remote link partner, then this bit remains a logic zero.
Receives valid FLP bursts from its remote link partner (thereby indicating that it can participate in the
auto-negotiation process), then the ICS1893CY-10 sets this bit to a logic one.
ICS1893CY-10 - Release
Copyright © 2007, Integrated Device Technology, Inc.
and
and
Section 7.1.4.2, “Latching Low
Section 7.1.4.2, “Latching Low
All rights reserved.
79
Chapter 7 Management Register Set
Bits”.)
Bits”.)
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