ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 129

• Manufacturer Part Number: ics1893cy-10
• Description: 3.3-v 10base-t/100base-tx Integrated Phyceiver
• Manufacturer: Integrated Device Technology

9.5.12 MII / 100M Stream Interface: Transmit Latency
ICS1893CY-10 Rev 1/07
TXEN
TXCLK
TXD
TP_TX
Table 9-19
periods consist of timings of signals on the following pins:
•
•
•
•
Figure 9-13
Table 9-19. MII / 100M Stream Interface Transmit Latency
† The IEEE maximum is 18 bit times.
Figure 9-13. MII / 100M Stream Interface Transmit Latency Timing Diagram
Period
†
unscrambled.
Time
TXEN
TXCLK
TXD (that is, TXD[3:0])
TP_TX (that is, TP_TXP and TP_TXN)
Shown
t1
t2
ICS1893CY-10 Data Sheet - Release
†
TXEN Sampled to MDI Output of First
Bit of /J/ †
TXD Sampled to MDI Output of First
Bit of /J/ †
lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
shows the timing diagram for the time periods.
Preamble /J/
Parameter
Copyright © 2007, Integrated Device Technology, Inc.
Preamble /K/
All rights reserved.
t1
t2
130
MII mode
100M Stream Interface
Conditions
Chapter 9 DC and AC Operating Conditions
Min.
–
–
Typ. Max.
2.8
6.1
7
3
Bit times
Bit times
Units