ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 131

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ics1893cy-10

Manufacturer Part Number
ics1893cy-10
Description
3.3-v 10base-t/100base-tx Integrated Phyceiver
Manufacturer
Integrated Device Technology
Datasheet

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9.5.14 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
ICS1893CY-10 Rev 1/07
Table 9-21
transmission. The time periods consist of timings of signals on the following pins:
Figure 9-15
Table 9-21. 10M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Figure 9-15. 10M MII Carrier Assertion/De-Assertion Timing Diagram
TXEN
TXCLK
CRS
Period
Time
TXEN
TXCLK
CRS
t1
t2
ICS1893CY-10 Data Sheet - Release
TXEN Asserted to CRS Assert
TXEN De-Asserted to CRS De-Asserted
lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex
shows the timing diagram for the time periods.
(Half-Duplex Transmission Only)
t1
Copyright © 2007, Integrated Device Technology, Inc.
Parameter
All rights reserved.
132
t2
Chapter 9 DC and AC Operating Conditions
Condi-
tions
Min.
0
0
Typ.
2
Max.
2
4
Bit times
Bit times
Units

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