ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 127

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ics1893cy-10

Manufacturer Part Number
ics1893cy-10
Description
3.3-v 10base-t/100base-tx Integrated Phyceiver
Manufacturer
Integrated Device Technology
Datasheet

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9.5.10 10M Serial Interface: Transmit Latency
ICS1893CY-10 Rev 1/07
(MDI)
P[3:0]TP_TX
10TXEN
10TCLK
10TD
Table 9-17
consist of timings of signals on the following pins:
Figure 9-11
Table 9-17. 10M Serial Interface Transmit Latency Timing
Figure 9-11. 10M Serial Interface Transmit Latency Timing Diagram
Period
Time
10TXEN (the 10M Serial Interface mapping of the 10M/100M MII TXEN pins)
10TCLK (the 10M Serial Interface mapping of the 10M/100M MII TXCLK pins)
10TD (the 10M Serial Interface mapping of the 10M/100M MII TXD0 pins)
TP_TX (the MDI mapping of the 10M/100M MII TP_TXP and TP_TXN pins)
t1
ICS1893CY-10 Data Sheet - Release
10TD Into TP_TX Out Delay
lists the significant time periods for the 10M Serial Interface transmit latency. The time periods
shows the timing diagram for the time periods.
Bit A
Parameter
Copyright © 2007, Integrated Device Technology, Inc.
Bit B
t1
All rights reserved.
128
10M Serial Interface
Conditions
Chapter 9 DC and AC Operating Conditions
Min.
Bit A
Typ.
0.8
Max.
1
Bit B
Bit times
Units

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