ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 75

• Manufacturer Part Number: ics1893cy-10
• Description: 3.3-v 10base-t/100base-tx Integrated Phyceiver
• Manufacturer: Integrated Device Technology

7.6.5.2 Technology Ability Field: Software Mode
7.6.6 Selector Field (Bits 4.4:0)
ICS1893CY-10 Rev 1/07
In Software mode (that is, the HW/SW pin is logic one), these TAF bits are Command Override Write bits.
The default value of these bits depends on the signal level on the HW/SW pin and whether the
Auto-Negotiation sublayer is enabled.
In Software mode, with the Auto-Negotiation Enable bit (bit 0.12) set to logic:
•
•
When its Auto-Negotiation Sublayer is enabled, the ICS1893CY-10 transmits its link capabilities to its
remote Link Partner during the auto-negotiation process. The Selector Field is transmitted based on the
value of bits 4.4:0. These bits indicate to the remote link partner the type of message being sent during the
auto-negotiation process. The ICS1893CY-10 supports IEEE Std 802.3, represented by a value of 00001b
in bits 4.4:0. The ISO/IEC 8802-3 standard defines the Selector Field technologies in Annex 28A.
Zero (that is, disabled), the ICS1893CY-10 does not execute the auto-negotiation process. Upon
completion of the initialization sequence, the ICS1893CY-10 proceeds to the Idle state and begins
transmitting IDLES. Two Control Register bits – the Data Rate Select bit (bit 0.13) and the Duplex Select
bit (bit 0.8) – determine the technology mode that the ICS1893CY-10 uses for data transmission and
reception. In this mode, the values of the TAF bits (bits 4.8:5) are undefined.
One (that is, enabled), the ICS1893CY-10 executes the auto-negotiation process and advertises its
capabilities to the remote link partner. The TAF bits (bits 4.8:5) determine the capabilities that the
ICS1893CY-10 advertises to its remote link partner. For the ICS1893CY-10, all of these bits 4.8:5 are set
to logic one, indicating the ability of the ICS1893CY-10 to provide these technologies.
ICS1893CY-10 - Release
Note:
1. The ICS1893CY-10 does not alter the value of the Status Register bits based on the TAF bits in
2. In this mode, an STA can alter the default TAF bit settings, 4.12:5, and subsequently issue an
register 4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the
capabilities of the ICS1893CY-10.
Auto-Negotiation Restart.
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
75
Chapter 7 Management Register Set